Emc Corporation

Eli Shagam

Natan Vishlitzky

Haim Kopylovitz

Yuval Ofek

Steven T McClure

Gilad Sade

Josef Ezra

Qun Fan

Robert DeCrescenzo

Jerome Cartmell

Avihu Goral

Erez Ofer

Ishay Kedem

David Shadmon

Scott B Gordon

Moshe Schreiber

A local area network includes a plurality of devices and a firewall for interfacing the LAN to a wide area network. In the LAN, each device generates a message packets for transmission over the network in which a time to live field contains an initial value that is preferably selected to be a function of the maximum path length for transfer of message packets within the local area network. Similarly, the firewall, when it receives message packets from the WAN for transmission to a device on the LAN provides in the time to live field an initial value that is preferably selected to be a function of the maximum path length for transfer of message packets within the local area network. When the firewall received a message packet from the LAN for transmission over the WAN, it provides a default initial value that is selected for use for message packets transmitted over the WAN in the time to live field, which typically will be significantly higher than the initial value that is used in the local area network. Since the initial time to live value used in the local area network is preferably selected to be a function of the maximum path length for transfer of message packets within the local area network, it can be much lower than the value that is typically used. This can reduce the bandwidth taken up by message packets that are in a loop in the local area network, which, in turn, can allow for increased bandwidth available for message packets that are being transferred through a portion of the loop but which are not themselves looping through the entire loop.

System and method for reducing bandwidth consumed by looping message packets in local area network

Accessing data memory includes writing data to a first memory location and to a second memory location in response to a request to write data to a memory address that corresponds to both locations, where the first and second memory locations are mirrored, in response to a request to read data from the memory address, reading data from the first memory location or the second memory location based on load balancing, and accessing data from the second memory location in response to a request to access data at the memory address when memory hardware corresponding to the first memory location has failed. Accessing the data memory may include requesting access to a specific one of the first and second memory locations. The memory address may contain a portion that is common to both the first memory location and the second memory location. Hardware coupled to the memory may cause data written using the memory address to be automatically written to the first memory location and the second memory location.

Mirrored memory

In a method for testing computer code, each branch that occurs within the machine-readable code is located. A first tracepoint is placed immediately after the beginning of the branch and a second tracepoint at the target address of each branch, each tracepoint generating an indicator. When the machine-readable code with the tracepoints is executed on the target computer, the method identifies those indicators that have been generated by their corresponding tracepoints, thereby permitting determination of those branches that the program control flow has not passed through. The test cases are modified to exercise the previously omitted branches, and the converted code is re-executed, until all branches have been properly exercised. The tracepoints are automatically eliminated after they have performed their intended function.

Software debugging tool

Handling a faulting memory of a pair of mirrored memories includes initially causing a non-faulting memory of the pair of mirrored memories to service all read and write operations for the pair of mirrored memories, determining that hardware corresponding to the faulting memory of the pair of mirrored memories has been successfully replaced to provide a new memory, in response to the new memory being provided, causing data to be copied from the non-faulting memory to the new memory while data is being read to and written from the non-faulting memory, and, in response to successful copying to the new memory, causing writes to be performed to both memories of the pair of mirrored memories and selecting one of the pair of mirrored memories for read operations when one or more read operations are performed. Handling a faulting memory may also include, in response to a write being performed to the non-faulting memory while data is being copied from the non-faulting memory to the new memory, causing the write to be performed to the non-faulting memory and the new memory.

Handling memory faults for mirrored memory

A method, system, and computer program product are disclosed for managing data in a cache. A first cache memory is provided that includes data. A second cache memory is provided that also includes data in which at least some of the data in the first cache memory is the same as at least some of the data in the second cache memory. In response to a request for data that is stored in both the first and second cache memories, one of the cache memories is chosen in accordance with an access balancing technique. The access balancing technique may include at least one of selection using round robin, and selection based on statistical analysis such as access frequency of the first and second cache memories. First and second access balancing techniques may be used for data accessed from the cache memories, which may comprise disk data and control data, such as data indicating whether data in the caches has been modified and is write pending.

Method, system and computer program product for managing data in a mirrored cache using an access balancing technique

A debugger mechanism to support multiple active targets and efficient switching between multiple active targets, in particular, heterogeneous targets, in a multiprocessing environment.

Debugging tool for efficient switching between targets in a multi-processor environment

A memory manager for use in connection with a memory comprises a memory access request receiver module, an address translation module and a memory access operation control module. The memory access request receiver module is configured to receive an access request requesting an access operation in connection with the memory, the access request including an address. The address translation module is configured to, (i) if the access request requests an access operation in connection with one of a plurality of sections of the memory, provide the address in the access request as an absolute address identifying at least one storage location in the one section; and (ii) if the access request requests an access operation in connection with another of said sections, generate an absolute address from the address provided in the access request, the address in the access request including a segment identifier and an offset, the address translation module being configured to process the segment identifier and offset to generate an absolute address identifying at least one storage location in the other of said sections. The memory access operation control module is configured to perform an access operation in connection with the memory using the absolute address generated by the address translation module.

Digital data storage subsystem including arrangement for increasing cache memory addressability

Managing data in cache includes providing data from a disk storage area to a first cache memory, providing data from the disk storage area to a second cache memory, where the first and second cache memories contain at least some data that is not stored in the other one of the cache memories, and writing the same data to both of the cache memories in response to the data being modified while stored in the cache memories. Managing data in a cache may also include subdividing the first cache memory into primary and secondary storage areas, subdividing the second cache memory into primary and secondary storage areas, where primary areas of the first cache correspond to secondary areas of the second cache and where secondary areas of the first cache correspond to primary areas of the second cache, and providing data from the disk storage area to the one of the cache memories having a corresponding primary storage area. Managing data in a cache memory may also include subdividing the disk storage area into a plurality of slots, where each of the slots corresponds to a primary area of one of the cache memories and to a secondary area of the other one of the cache memories.

Fault tolerant dual cache system

The invention relates to a data processing system and method wherein a data processing system is connected to at least two busses, each of which is connected to a memory system. Controllers connected to one of the buses monitor the write operations at each other bus. The monitoring controllers are each connected to less then all of the lines of the &ldquo;other bus&rdquo; and continuously update their cache memories to reflect and maintain the integrity of the data in the cache memory.

Cache mechanism for shared resources in a multibus data processing system

A distributed computer system includes a plurality of computer nodes, including conventional digital computer systems, mass storage subsystems, servers and the like, and a common event log. The common event log includes a plurality of storage locations for storing common event log entries. Each computer node performs processing operations in connection with a program, and generates, at selected points in its program, an event log entry including status information representing status of the computer node at the point at which the log entry was generated, the computer nodes storing the event log entries which they generate in the common event log contemporaneous with the generation thereof. As a result, the event log entries are stored in the common event log in the order in which the computer nodes reach the points in their respective programs. The common event log includes a buffer comprising a plurality of storage locations, and the location at which an entry is to be stored is pointed to by a write pointer. In one embodiment, the various computer nodes are interconnected by a common bus. When a computer node is to store a new entry in the common event log, it retrieves the write pointer, increments it and restores it in an atomic &ldquo;read/modify/write&rdquo; operation over the bus, and thereafter may use the write pointer which it retrieved to store the entry in the common event log.

System using a common and local event logs for logging event information generated by plurality of devices for determining problem in storage access operations

Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to blocks of contiguous storage locations, such as logical volumes on the physical disk storage devices to obtain disk utilization information. The disk utilization information provides a selection of one block pair. After testing to determine any adverse effect of making that change, an exchange is made to more evenly distribute the loading on individual physical disk storage devices. The exchange involves the use of a pair of specially configured logical volumes that receive copies of the data to be exchanged, allow a reconfiguration of the blocks in the block pair and the transfer of the data back to the other blocks in the block pair to effect the exchange.

Method for transparent exchange of logical volumes in a disk array storage device

The invention relates to a method and apparatus for debugging software running in a target machine. A debugging set-up script is created in a host machine which defines trace point locations, and the variables to be returned to the host machine. The method sends the trace point locations and variables to the target machine where a stub program running in the target machine effects the modification of a software program in the target machine by inserting traps at the trace points. Data is collected using the stub program to ascertain variable values when a trace point is hit and the acquired variable data are stored in the target machine in a target machine buffer memory. The collected data is sent, at the request of the host machine, or at the end of a predetermined time, or when a pass-count is reached or at a time set by the target machine, to the host machine without stopping or interrupting operation of the target system.

Online debugging and tracing system and method

An apparatus for defragmenting disks by incorporating a copy function in the logic controlling a disk, so that a disk can be instructed to copy the contents of tracks from one area to another on the disk without requiring a series of data transfers between the disk and the host computer to which it is assigned. Conventional defragmentation techniques can be used to determine which files need to be defragmented and how much contiguous free space is available on the disk. Once this has been determined, the present invention enables the defragmentation program to send copy commands to the disk to cause the copy function in the logic controlling the disk to perform the data transfers, thus freeing up the host computer to perform other processing until the logic controlling the disk signals completion of the copy function's operation.

Method and apparatus for defragmenting a storage device using a copy function in the device control logic

A method and apparatus for debugging the source code using the source code debugger includes the following steps. A script generator is provided to receive source code instructions. Executing the script generator includes reading each source code instruction and generating, based on the type of instruction, a debugging script. The debugging script includes a specification of trace points. The debugging script is then provided to the source code debugger.

Source code debugging tool

A method for counting the number of bits which are set to binary '1' in a word of length 2.sup.n includes generating a first mask of length 2.sup.n having alternating sequences of '1''s and '0''s, each sequence having a length 'x' (the length 'x' initially having a value of 1), and generating a second mask of length 2.sup.n by forming the complement of the first mask. Logical AND operations using the word and each of the first and second masks are performed to generate first and second intermediate words, respectively. That one of the first and second intermediate words having been ANDed with one of the first and second masks having a '0' in its least significant bit position, is shifted 'x' number of bit positions to generate a shifted intermediate word. The shifted intermediate word and the other of the first and second intermediate words are arithmetically added to generate a bit-counted word of 2.sup.n length representing the number of bits in the word set to binary '1' from the bit-counted word. The value of 'x' is doubled and the method is repeated 2.sup.n iterations.

Growing community of inventors

Brookline, MA, United States of America

Eli Shagam