Saifun Semiconductors Ltd.

Spansion Israel Ltd

Infinite Memory Ltd.

Infinite Memories Ltd.

Infinte Mormories Ltd.

Eli Lusky

Boaz Eitan

Guy Cohen

Assaf Shappir

Yoav Yogev

Eduardo Maayan

Rustom Irani

Amir Gabai

Ilan Bloom

Aner Arussi

The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and reading algorithms are presented.

Continuous address space in non-volatile-memories (NVM) using efficient management methods for array deficiencies

A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage with respect to at least one reference cell activated at a voltage having its associated stored reference gate voltage value.

Method of handling reference cells in NVM arrays

OTP Data storage die and device consisting of novel OTP (One-Time-Programming) NVM (Non-Volatile-Memory) die is disclosed. The OTP Data storage device can be used in typical host applications with standard interface protocols and file system. The novel OTP memory is a dual memory with both RAM (random access memory) capability and NAND Flash like interface. These features enable to achieve efficient management capabilities and dense array for the OTP data storage device.

Non-volatile dual memory die for data storage devices

The invention provides a method of managing data updates in DOS-based data storage device having an OTP memory die that includes a code region having a first memory capacity and a code region access resolution and a data region having a second memory capacity and a data region access resolution. The second memory capacity is larger than the first memory capacity and the code region access resolution is finer than the data region access resolution. The method includes chronologically writing a log entry in the code region indicating the change in FAT and root directory for each change in user data written in the data region.

Method for using an OTP storage device

A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Non-volatile memory structure and method of fabrication

A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

Reading array cell with matched reference cell

A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.

Method of erasing non-volatile memory cells

Operating array cells with matched reference cells

An NROM (nitride read only memory) cell, which is programmed by channel hot electron injection and erased by hot hole injection, includes a charge trapping structure formed of: a bottom oxide layer, a charge trapping layer; and a top oxide layer. The bottom oxide layer is no thicker than that which provides margin stability.

Threshold voltage shift in NROM cells

A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.

Protection of NROM devices from charge damage

A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with a group of memory cells of a non-volatile memory cell array, allowing correct reading of the group of history cells, selecting a memory read reference level according to the first read reference level, and reading the non-volatile memory array cells.

Method for reading non-volatile memory cells

A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving the same sensing accuracy with improved read disturb immunity.

A method for erasing a bit of a memory cell in a non-volatile memory cell array, the method comprising applying an erase pulse to at least one bit of at least one memory cell of the array, waiting a delay period wherein a threshold voltage of the at least one memory cell drifts to a different magnitude than at the start of the delay period, and after the delay period, erase verifying the at least one bit to determine if the at least one bit is less than a reference voltage level.

Growing community of inventors

Tel Aviv, Israel

Eli Lusky