Gsi Technology, Inc.

Zikbit Ltd.

Mikamonu Group Ltd.

Gsi Technology Israel Ltd.

Other

Eli Ehrman

Avidan Akerib

Chao-Hung Chang

Mu-Hsiang Huang

Bob Haig

Oren Agam

Moshe Meyassed

Moshe Lazer

Lee-Lean Shu

Patrick Chuang

Dan Ilan

Yoav Lavi

Yair Alpern

Elona Erez

Josh Meir

A deduplication system includes a similarity searcher, a difference calculator, and a storage manager. The similarity searcher searches for a similar fingerprint in a database storing a plurality of local sensitive fingerprints, resembling a new fingerprint of a new block. The difference calculator computes a difference block between the input block and a similar block associated with the found similar fingerprint, and the storage manager updates the database with the new fingerprint and stores the difference block, if not empty, in a store. A method for deduplication includes searching in a database, storing a plurality of local sensitive fingerprints, a similar fingerprint, resembling a new fingerprint of a new block, calculating a difference block between the input block and a similar block associated with the similar fingerprint, if found, updating the database with the new fingerprint and storing the difference block, if it is not empty, in a storage unit.

Deduplication of data via associative similarity search

A method for selecting items one by one from a set of items elected from a large dataset of items includes determining whether or not a density of the set is sparse. If the density is sparse, the method includes repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set. If the density is not sparse, the method includes performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set.

One by one selection of items of a set

A memory device includes a plurality of memory units and a global responder (RSP) unit. Each memory unit includes a memory array of memory cells arranged in rows and columns, and an RSP unit. The memory array receives horizontal input data rotated for storage as data candidates in columns of the array. At least one of the rows is a calculation row receiving per-bit-line Boolean AND operations between bits of a marker row and bits of a row of data of the data candidates. The RSP unit includes wired-OR circuitry operative on the calculation row to generate a responder signal indicating whether there is one cell in the calculation row having a predefined value identifying a data candidate in the memory array. The global RSP unit receives multiple responder signals, one from at least two of the RSP units, and performs Boolean OR operations on the multiple responder signals.

Global responder signal circuitry for memory arrays

A method for machine learning includes extracting features from a training set of inputs, wherein each input generates a feature set and each the feature set forms a neural network key. The method includes arranging the keys in an in-memory computational layer such that the distance between any pair of keys corresponding to similar inputs is as close as possible while keys for a pair of dissimilar inputs have differing values as far apart as possible, wherein each of the keys has a fixed size. The method also includes searching through the dataset using an in-memory K-nearest neighbor unit to find K keys similar to a query key, the searching occurring in a constant amount of time as a function of the fixed size and irrespective of a size of the dataset.

Integrating a memory layer in a neural network for one-shot learning

An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.

A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Computational memory cell and processing array device using the memory cells for XOR and XNOR computations

A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of the data candidates, performing a Boolean OR operation between the marker bits in the subsequent row of marker bits to generate a subsequent RSP value, identifying the extreme value from among the plurality of data candidates when there is only one marker bit having a value of 1 in the subsequent row of marker bits coinciding with when said subsequent RSP value is a 1, and if the identifying is false, repeating the computing on a row of next most significant bits, performing and identifying until the identifying is true.

Memory device for determining an extreme value

A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Write data processing methods associated with computational memory cells

A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Read data processing circuits and methods associated with computational memory cells

A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Results processing circuits and methods associated with computational memory cells

A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of 'n' bit lines.

Write data processing circuits and methods associated with computational memory cells

A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.

Responder signal circuitry for memory arrays finding at least one cell with a predefined value

A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set. An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.

A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. The method includes arranging the multi-bit binary numbers such that each bit n of each said multi-bit binary number is located in a different row n of an associative memory array, starting from a row storing a most significant bit (MSB), adding an indicator to the set for each multi-bit binary number having a bit with an extreme value in the row and continuing the adding until said set contains k indicators.

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Eli Ehrman