Intel Corporation

Elena Agranovsky

Eli Elik Kupermann

Adrian R Pearson

Suryaprasad Kareenahalli

Bing Zhu

Rajasekaran Andiappan

Yang Huang

Yehiel Shilo

Yael Yanai

Christian Soby

Amit Kimelman

Chen-Hsun Wu

Tomas Winkler

Marlon D Bada

Multi-mode protected memory in accordance with the present description includes a permanent mode and a transient mode of operation. In one embodiment of the permanent mode, an authentication key is programmable once and a write counter is not decrementable or resettable. In one embodiment of the transient mode, an authentication key may be programmed many times and a write counter may be reset many times. Other features and advantages may be realized, depending upon the particular application.

Multi-mode protected memory

Embodiments of the present disclosure provide techniques for sensor testing for computing devices during initial movement of the device, such as movement on a manufacturing line. In one instance, a device with integral sensor testing during initial movement of the device may include a plurality of sensors and a sensor test block coupled with the plurality of sensors, to detect, collect and/or report readings provided by at least some of the sensors in response to movement of the device between at least a first test station and a second test station. Other embodiments may be described and/or claimed.

Testing of device sensors on a manufacturing line

Described is an apparatus comprising: a processor operable to execute a virtual machine manager (VMM) which is to manage a virtual machine (VM) for a hardware intellectual property (IP) block; a communication fabric; and a hardware IP block coupled to the processor via the communication fabric, wherein the hardware IP block is to be coupled to a first set of one or more sensors, and wherein the VM and the hardware IP block are operable to process data collected from the first set.

Low power sensing apparatus and method using a combination of virtual machine and dedicated hardware intellectual property IP block

In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.

Dynamically controlling power management of an on-die memory of a processor

Growing community of inventors

Jerusalem, Israel

Elena Agranovsky