Texas Instruments Corporation

Eleazar Walter Kenyon

Arlo James Aude

Kumar Anurag Shrivastava

Michael Gerald Vrazel

A latching sense amplifier includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a first output node, a second output node, a pull-up circuit, and a pull-down circuit. The pull-up circuit includes a first transistor, a second transistor, and a latch circuit. The first transistor is configured to pull up the first output node. The second transistor is configured to pull up the second output node. The latch circuit is configured to control the first transistor and the second transistor. The pull-down circuit includes a latch circuit configured to pull-down the first output node based on a voltage of the second output node.

Latching sense amplifier

An LC oscillator architecture in which an LC tank is driven by a negative resistance element (amplifier) including first and second Vbe/Vgs multipliers cross-coupled to the LC tank. Each Vbe/Vgs multiplier circuitry including a transistor with a control terminal as a negative input, a reference terminal as a positive input, and an output terminal, a shunt resistance connected between the control terminal and the reference terminal, a series resistance connected between the control terminal and the output terminal for one of the same transistor or the other transistor, and a shorting capacitance connected between the control terminal of the transistor, and the output terminal of the transistor of the other Vbe/Vgs multiplier. An example application is an LC VCO, such as for a PLL, CDR, or retimer.

LC oscillator driven by a negative resistance element

A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.

Signal conditioning in a serial data link

A signal detection circuit includes a signal input terminal, a rectifier circuit, a comparator circuit; a current source, and a comparator output terminal. The rectifier circuit is coupled to the signal input terminal and is configured to receive an input signal and generate a rectified signal based on the input signal. The comparator circuit is coupled to the rectifier circuit and is configured to receive a common mode signal and to generate a difference current based on a difference of the common mode signal and the rectified signal. The current source is coupled to the comparator circuit and is configured to generate a reference current. The comparator output terminal is configured to provide an output signal based on a difference of the reference current and the difference current.

Signal detection circuit

A data correction filter includes an equalizer circuit, first, second, and third asynchronous comparators, an error amplifier, a multiplexer, a delay circuit, first and second exclusive-OR gates, and first and second integrator circuits. The first asynchronous comparator is coupled to the equalizer circuit. The second and third asynchronous comparators are coupled to the equalizer circuit and the error amplifier. The multiplexer is coupled to the first, second, and third asynchronous comparators. The delay circuit is coupled to the first asynchronous comparator. The first exclusive-OR gate is coupled to the delay circuit and the multiplexer. The second exclusive-OR gate is coupled to the first asynchronous comparator and the multiplexer. The first integrator circuit is coupled to first exclusive-OR gate and the equalizer circuit. The second integrator circuit is coupled to the second exclusive-OR gate and the error amplifier.

Asynchronous data correction filter

A sub-rate (such as half-rate I and Q) phase-interpolator based CDR architecture is configured to receive serial data signals and multiple sub-rate clock signals (such as generated by a VCO either integrated or external). The CDR includes multiple phase interpolators to generate, from respective sub-rate clock signals, respective PI (phase-interpolated) sub-rate clock signals. A CDR loop is configured to receive the input data and the PI sub-rate clock signals, and to generate multiple PI control signals, each to control a respective phase interpolator to align the PI sub-rate clock signals to the data edges. A skew-correction loop includes skew detection circuitry to generate a skew error signal from the PI sub-rate clock signals corresponding to a skew error between the PI sub-rate clock signals, and skew-correction offset circuitry to generate, from the skew error signal, a skew-correction offset signal to modify a selected PI control signal.

Sub-rate phase interpolator based clock data recovery architecture with phase skew correction

A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

Peak detector circuit

A receiver module includes a clock recovery circuit and a decision feedback equalizer (DFE) circuit. The DFE circuit includes a data feedback loop configured to sample an input data stream combined with equalization values based on a first clock signal. The DFE circuit also includes an edge feedback loop configured to sample the input data stream combined with equalization values based on a second clock signal. The clock recovery circuit is configured to determine a phase error between a receiver clock signal and a target clock signal based on output samples from the data feedback loop and the edge feedback loop.

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Tucker, GA, United States of America

Eleazar Walter Kenyon