Hewlett-packard Company

Eldon C Cornish

Kenneth Rush

Rodney H Orgill

Joe K Millard

Steve Draving

An electrical interconnect between a plurality of output nodes of a first integrated circuit (IC) and a plurality of input nodes of a second IC, the interconnect. A first bond pad located on the first integrated circuit is coupled to the output nodes. A second bond pad located on the second integrated circuit is coupled to the input nodes. A first digital-to-analog converter located on the first integrated circuit and having an output coupled to the first bond pad receives a plurality of binary inputs from the output nodes of the first integrated circuit. A first analog-to-digital converter is located on the second integrated circuit and coupled to the second bond pad and has an output line coupled to each of the plurality of input nodes of the second IC.

Voltage multiplexed chip I/O for multi-chip modules

A circuit for coupling ECL level logic signals to NMOS circuitry first translates the ECL logic swing from the range of -1.6 v to -0.8 v up to the range of about +0.5 v to +1.3 v. This is done by driving the source of an enhancement device with the ECL input signal. This has the further benificial effect of compensating for temperature changes and process related variables. The level shifted signal is then applied to a gain stage for amplification and delivery to the using circuits. If the ECL input signal is available in complementary form then the complement can be used to drive the source of the gain stage; otherwise it should be connected to V.sub.ref of the ECL circuitry.

ECL to NMOS converter

A low-power high-speed static latch with super buffer outputs is implemented as an MOS integrated circuit by providing resistive cross coupling from those super buffer outputs to inputs through depletion devices that serve in the place of high valued resistors. The resulting static latch exhibits only one gate delay from input to output, has only one enhancement device at a time on, and may be used to create a static MOS shift register.

Static MOS super buffer latch

An oscilloscope has an additional vertical display mode to enable the display of the trigger signal, activating the sweep generating circuit, simultaneously with the display of the normal vertical channels. The triggering source, level, slope and subtle time relationships can be verified and examined continuously and concurrently with the measurements upon the normal vertical channels. The displayed trigger signal is in correct time relationship with the normal vertical channels and the trigger level threshold is identified.

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Colorado Springs, CO, United States of America

Eldon C Cornish