Marvell Israel (misl) Ltd.

Eldad Bar-Lev

Ofer Benjamin

Dan Azeroual

Aaron Landau

Aspects of the disclosure provide a printed circuit board (PCB) system that includes an integrated circuit (IC) package, a first PCB and a PCB module. The IC package has a package substrate and an IC chip that is coupled to a top surface of the package substrate. The first PCB is configured to electrically couple with first contact structures that are disposed on a bottom surface of the package substrate. The PCB module includes a second PCB and one or more electronic components electrically coupled to the second PCB. The PCB module is configured to electrically couple with second contact structures that are disposed on the top surface of the package substrate.

PCB module on package

A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.

Optimal sampling of data-bus signals using configurable individual time delays

Aspects of the disclosure provide a printed circuit board (PCB) structure. The PCB structure includes a plurality of dielectric layers including an outer layer, a second layer disposed immediately below the outer layer, at least one first power plane disposed on at least one first internal layer of the PCB structure, and at least one first ground plane disposed on at least one second internal layer of the PCB structure. The PCB structure further includes an array of buried vias passing through at least the second layer configured to respectively connect power pads disposed on the second layer to the at least one first power plane and to connect ground pads disposed on the second layer to the at least one first ground plane. The array of buried vias is defined by columns of pads in which a respective column includes either power pads or ground pads, columns of power pads alternate with columns of ground pads, and pads of at least one of a column of power pads and a column of ground pads are staggered with respect to other pads of the at least one of the column of power pads and the column of ground pads. The PCB structure further includes an array of outer layer vias passing through the outer layer and configured to provide an electrical connection between one or more circuit components disposed on the outer layer and the second layer.

Power delivery network in a printed circuit board structure

Some of the embodiments of the present disclosure provide a method including: communicating, by a first pin of an integrated circuit, with a device over a communication link, wherein the first pin is associated with a first impedance; selecting a plurality of impedance values for the first impedance; for ones of the plurality of impedance values, (i) transmitting a corresponding digital signal from the first pin over the communication link and (ii) generating a corresponding signal eye opening for the corresponding digital signal, such that a plurality of signal eye openings corresponding to a plurality of digitals signals for the corresponding plurality of impedance values are generated; comparing the plurality of signal eye openings; selecting a first impedance value of the plurality of impedance values; and transmitting signals over the communication link, with the first impedance being tuned to the first impedance value.

Impedance and duty cycle calibration in a driver circuit and a receiver circuit

Methods and apparatuses for processing systems capable of compensating for data skew are disclosed. An example apparatus can include delay circuitry that includes a plurality of delay devices each being individually adjustable to produce an individual delay for each data line with each data line including branches of different lengths leading to different memory devices, and memory control circuitry coupled to the delay circuitry and configured to determine, for each data line, an individual delay based on an optimized critical window, the optimized critical window being based on multiple chip select signals.

Apparatus and method to compensate for data skew for multiple memory devices and adjust delay for individual data lines based on an optimized critical window

Some of the embodiments of the present disclosure provide an integrated circuit communicating with a device over a multi-pin parallel bus, the integrated circuit comprising: at least a first pin and a second pin to communicate with the device over the multi-pin parallel bus; and an impedance tuning module disposed in the integrated circuit and configured to tune an impedance value of a first impedance associated the first pin separately from tuning an impedance value of a second impedance associated with the second pin.

Impedance calibration in a driver circuit and a receiver circuit

Aspects of the disclosure provide an integrated circuit (IC) that includes a processing unit and a signal-terminal matching circuitry. The processing unit is configured to communicate with an external memory device through conductive couplings that electrically couple terminals of an IC external interface respectively with terminals of the external memory device. The external memory device is disposed on a circuit substrate separate from the IC. The signal-terminal matching circuitry is configured to match memory control signals to the terminals of the IC external interface based on the external memory device.

Method and apparatus for memory control

Systems and methods are provided a circuit interconnect. In one embodiment of the disclosure, the circuit interconnect includes a dielectric layer. A parallel synchronous bus is disposed on the dielectric layer. The parallel synchronous bus includes at least four conductive traces. The conductive traces are non-uniformly spaced from one another along a portion of the bus where the conductive traces are physically aligned in parallel so that crosstalk interference among the conductive traces is equalized across the conductive traces.

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Kiryat Tivon, Israel

Eldad Bar-Lev