International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Advanced Micro Devices Corporation

Globalfoundries U.S. 2 LLC

Globalfoundries Singapore Pte, Lte.

Elbert Emin Huang

Satyanarayana Venkata Nitta

Sampath Purushothaman

Daniel C Edelstein

Griselda Bonilla

Benjamin David Briggs

Matthew Earl Colburn

Christopher J Penny

Takeshi Nogami

Shom Ponoth

Stephen McConnell Gates

Jeffrey Curtis Hedrick

David V Horak

Timothy Joseph Dalton

Andrew Herbert Simon

Muthumanickam Sankarapandian

Robert Dennis Miller

Dirk Pfeiffer

David Lee Rath

Deepika Priyadarshini

Joe Lee

Raghuveer Reddy Patlolla

Theodorus E Standaert

Charles W Koburger, Iii

Son Van Nguyen

Ronald G Filippi

Naftali Eliahu Lustig

Michael Wayne Lane

Jessica M Dechene

Lawrence Alfred Clevenger

Jeffrey P Gambino

Thomas M Shaw

Terry Allen Spooner

Willi Volksen

Cornelius Brown Peethala

Christy Sensenich Tyberg

Chih-Chao Yang

Anthony K Stamper

Carl John Radens

John Anthony Fitzsimmons

Vincent James McGahay

Edward Crandal Cooney, Iii

Samuel S Choi

Satya Venkata Nitta

Lee Matthew Nicholson

Sujatha Sankaran

Katherine Lynn Saenger

Teddie Peregrino Magbitang

Kaushik Arun Kumar

Kelly Malone

Nicholas C Fuller

Qinghuang Lin

Hosadurga K Shobha

Craig Jon Hawker

Katherina E Babich

Maheswaran Surendra

Charles Thomas Rettner

Douglas C La Tulipe, Jr

Victor Yee-Way Lee

Arpan Pravin Mahorowala

Bruce Bennett Doris

James L Hedrick

Alfred Grill

Baozhen Li

Russell Alan Budd

Junjing Bao

John Christopher Arnold

Timothy A Brunner

David Robert Medeiros

Vivekananda P Adiga

William J Cote

Chao-Kun Hu

Dan Moy

David C Mckay

Stephan Alan Cohen

Paul Stephen McLaughlin

Geraud J Dubois

Yan Zun Li

Ghavam G Shahidi

Sivananda K Kanakasabapathy

Kenneth Parker Rodbell

Wai-Kin Li

Roy Rongqing Yu

Xiao Hu Liu

Robert L Wisnieff

Chandrasekhar Narayan

Fen Chen

Sean David Burns

David L Questad

Shyng-Tsong Chen

Gregory Breyta

Li-Wen Hung

Philip Joseph Oldiges

Martin O Sandberg

Nicholas C M Fuller

Xinlin Wang

William Francis Landers

Eric Gerhard Liniger

Ravi Prakash Srivastava

Daniel Rugar

Devices and/or computer-implemented methods to facilitate a programmable and/or reprogrammable quantum circuit are provided. According to an embodiment, a device can comprise a superconducting coupler device having a superconducting fuse device that is used to alter the coupling of a first quantum computing element and a second quantum computing element.

Programmable and reprogrammable quantum circuit

One or more systems, devices, methods of use and/or methods of fabrication provided herein relate to a superconducting device that can be operated with minimal electric field energy coupling at surface layers of the superconducting device and/or that can have a small footprint. According to one embodiment, a device can comprise a Josephson junction located between a first capacitor portion and a second capacitor portion of a capacitor, wherein at least a trenched section of the first capacitor portion is located beneath a surface of a substrate, and wherein at least a trenched section of the second capacitor portion is located beneath the surface of the substrate. According to another embodiment, a device can comprise a capacitor disposed within a substrate layer and the capacitor comprising a pair of material-filled trenches in the substrate layer, and a Josephson junction coupled to the capacitor.

Quantum circuit with trench capacitor

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Selective recessing to form a fully aligned via

Techniques regarding lithographic processes for fabricating Josephson junctions are provided. For example, one or more embodiments described herein can comprise a method that can include depositing a first resist layer onto a second resist layer. The first resist layer can include a bridge portion that defines an opening for forming a Josephson junction. The method can also comprise depositing a third resist layer onto the bridge portion. The third resist layer can shield the opening from an angled deposition of a superconducting material during fabrication of the Josephson junction.

Lithography for fabricating Josephson junctions

An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

Self-forming barrier for use in air gap formation

A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

Low aspect ratio interconnect

A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.

Interconnect structures with fully aligned vias

Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

Air gap and air spacer pinch off

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Carmel, NY, United States of America

Elbert Emin Huang