International Business Machines Corporation

Ekmini Anuja De Silva

Indira P Seshadri

Nelson M Felix

Ashim Dutta

Yann Mignot

Dario Leonardo Goldfarb

Andrew Mark Greene

Yongan Xu

Ruilong Xie

Chi-Chun Liu

Sivananda K Kanakasabapathy

Rudy J Wojtecki

Stuart A Sieg

John Christopher Arnold

Chih-Chao Yang

Fee Li Lie

Lawrence Alfred Clevenger

Ruqiang Bao

Su Chen Fan

Gauri V Karve

Kangguo Cheng

Peng Xu

Zhenxing Bi

Hosadurga K Shobha

Nicole A Saulnier

Nicolas J Loubet

Oleg Gluschenkov

Marc Adam Bergendahl

Daniel Sanders

Muthumanickam Sankarapandian

Juntao Li

Chen Zhang

Wenyu Xu

Eric R Miller

Cheng Chi

Dexin Kong

Tenko Yamashita

Chanro Park

Julien Frougier

Michael Rizzolo

Benjamin David Briggs

Jingyun Zhang

Christopher J Penny

Hsueh-Chung Chen

Ratnam Sooriyakumaran

Koichi Motoyama

Chun Wing Yeung

Cornelius Brown Peethala

Gregory Breyta

Michael P Belyansky

Linda Karin Sundberg

Jing Guo

Praveen Joseph

Jennifer Church

Abraham Arceo De La Pena

Luciana Meli Thompson

Dominik Metzler

Leigh Anne H Clevenger

Tao Li

Karen Elizabeth Petrillo

Yi Song

Siva Kanakasabapathy

Cody John Murray

Luciana Meli

Jay William Strane

Daniel A Corliss

Tsung-Sheng Kang

Bharat Kumar

Derren Neylon Dunn

Kisup Chung

Jing Sha

Gangadhara Raja Muthinti

Mona Abdulkhaleg Ebrish

Kristin Schmidt

Matthew T Shoudy

Isabel Cristina Chu

Romain Lallement

Noel Arellano

Alex Joseph Varghese

Dallas M Lea

Veeraraghavan S Baskar

Yann A M Mignot

Somnath Ghosh

Christopher Frederick Robinson

Ardasheir Rahman

Daniel Schmidt

Yasir Sulehria

Alex Richard Hubbard

Isabel C Estrada-Raygoza

Indira P V Seshadri

Noah F Fine Nathel

Allen H Gabor

Hoa D Truong

Hao Tang

Robin Hsin Kuo Chao

William Dinan Hinsberg

Luisa Dominica Bozano

Adra Carr

Martha Inez Sanchez

Shanti Pancharatnam

Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.

Vertically stacked fin semiconductor devices

A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Fabrication of embedded memory devices utilizing a self assembled monolayer

Embodiments of the invention include a dielectric reflow technique for boundary control in which a first layer is deposited on a first transistor region and a second transistor region, the first and second transistor regions being adjacent. A dielectric layer is formed to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location. In response to removing a portion of the first layer on the first transistor region, the dielectric layer protecting the second transistor region is reflowed such that at least a reflowed portion of the dielectric layer extends beyond the first location.

Dielectric reflow for boundary control

A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

Additive interconnect formation

Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.

Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via

A method of forming a multi color resist structure includes providing a substrate including an underlayer material; forming a first organic planarizing layer on the substrate; forming a first anti reflecting layer on the first organic planarizing layer, forming and developing a first patterned resist on the first anti reflecting layer; forming a second organic planarizing layer on the first anti reflecting layer and on the first patterned resist; forming a second anti reflecting layer on the second organic planarizing layer and forming and developing the second patterned resist, wherein the first patterned resist is a non-chemically amplified resist (n-CAR) or metal resist and the second patterned resist is CAR organic resist.

Litho-litho-etch (LLE) multi color resist

A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.

Polymer brush adhesion promoter with UV cleavable linker

A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

Subtractive patterning of interconnect structures

A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.

Vertical field effect transistor with crosslink fin arrangement

The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.

Metal cut patterning and etching to minimize interlayer dielectric layer loss

Techniques for selective CD shrink for source and drain contact trench to optimize FET device performance are provided. In one aspect, a semiconductor FET device includes: at least one gate; source and drains on opposite sides of the at least one gate; recesses in the source and drains; and metal contacts disposed over the source and drains and in the recesses, wherein the metal contacts are in direct contact with a bottom and sidewalls of each of the recesses in both a first direction and a second direction, wherein the first direction is perpendicular to the at least one gate, and wherein the second direction is parallel to the at least one gate. A method of forming a semiconductor FET device is also provided.

Selective shrink for contact trench

An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances.

Forming self-aligned multi-metal interconnects

A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.

Via CD controllable top via structure

A semiconductor device is provided. The semiconductor device includes a bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer, the gate stack including a work function metal (WFM) layer, a channel fin formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed in a gate landing area over the gate stack, a second ILD layer formed in an area other than the gate landing area, and a WFM encapsulation layer formed between the first ILD layer and the second ILD layer, and formed on sidewalls of the gate stack.

Vertical transport field-effect transistor with gate patterning

Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.

Alternating copolymer chain scission photoresists

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Slingerlands, NY, United States of America

Ekmini Anuja De Silva