Micron Technology Incorporated

Sandisk Technologies Inc.

Ekamdeep Singh

Ashish Ghai

Lakshmi Kalpana Vakati

Chang Hua Siau

Scott Anthony Stoller

Dheeraj Srinivasan

Mark Shlick

Pitamber Shukla

Chun Sum Yeung

Gopinath Balakrishnan

Trismardawi Tanadi

Srikar Peesari

Jeffrey Ming-Hung Tsai

Robert W Mason

Kapil Verma

Lu Tong

Yuvaraj Krishnamoorthy

Kalpana Vakati

Francis Chee Khai Chew

Chai Chuan Yao

Sheng Huang Lee

Matthew Ivan Warren

Wai Leong Chin

Lawrence Dumalag

Maythin Uthayopas

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.

Managing defective blocks during multi-plane programming operations in memory devices

Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

Multiple plane programming with quick plane programming termination and lagging plane boosting

A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.

Wordline leakage test management

Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.

Leakage current detection in 3D memory

To prevent data loss due to latent defects, a non-volatile memory system will use a leakage detection circuit to test for small amounts of leakage that indicate that the memory is susceptible to failure.

Non-volatile memory with in field failure prediction using leakage detection

Growing community of inventors

San Jose, CA, United States of America

Ekamdeep Singh