Asahi Kasei Microdevices Corporation

Eizo Ichihara

Shintaro Kawazoe

Yusuke Kai

Provided is a signal processing system including: an adaptive decimation filter apparatus which has a decimation filter which outputs an output signal obtained by down-sampling an input signal, and an aliasing noise detection unit which detects a magnitude of aliasing noise, which is folded back to a frequency lower than a Nyquist frequency in the output signal of the decimation filter by the down-sampling; and a signal processing apparatus which has a filter control unit which adjusts an order of the decimation filter on the basis of the magnitude of the aliasing noise, and an adaptive filter unit which performs filter processing on the output signal of the decimation filter.

Signal processing system, signal processing method, and non-transitory computer readable medium

Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.

Ad converter

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider () for feeding back an output of a VCO () of an output stage to a preceding stage is generated using an error signal from an accumulator (). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector () are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider () is suppressed.

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Tokyo, Japan

Eizo Ichihara