Motorola Corporation

Freescale Semiconductor,inc.

Eitan Zmora

Michael Priel

Dror Halahmi

David Galanti

Anton Rozen

Dan Kuzmin

Kevin L Kloker

Moshe Anschel

Ziv Zamsky

Natan Baron

Kostantin Godin

Avner Goren

Noam Sivan

Yair Orbach

Yacov Efrat

Hagai David

Dan Kuzman

Chen Goldenberg

Leonid Rabinovich

A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

Method and a computer readable medium for performing static timing analysis of a design of an integrated circuit

A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range.

Device and system for reducing noise induced errors

A method for sharing charge between IO circuits, the method includes providing an integrated circuit that comprises multiple IO circuits, each comprising an IO pad. The method is characterized by including: determining to share a charge between multiple IO circuits; and sharing charge between the multiple IO circuits by coupling the multiple IO circuits to a shared circuit that is characterized by a state that reflects multiple iterations of sharing charge operations.

Device and method for sharing charge

A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapted to: (i) provide to the first logic, a circuit write value during a circuit writing period and during an idle period that follows the circuit writing period and ends when another circuit is allowed to write; and (ii) provide a default value when another circuit is allowed to write; and wherein the first logic is adapted to alter a state of the first bus in response to a change between two consecutive circuit write values.

Non-high impedence device and method for reducing energy consumption

Dynamic RAM in a microprocessor system

An apparatus (12) and method (80, 120) is described for reducing power consumption in a system (10) having subsystems (34). A controller (40, 40', 40') detects the occurrence of a repetitive operation (62). The subsystems (34, 38) or a power down controller (39) detect (86, 128), whether a subset (60i) of the subsystems (34) is or is not participating in the repetitive operation (62). This preferably occurs during the first iteration (661-662) of the repetitive operation (62). Power controls (36) in or coupled to (39) the subsystems (34), reduce the power consumption of this subset (60i) of the subsystems (34) until the repetitive operation (62) is completed (642), whereupon power thereto is restored (114, 190). In the event of an interrupt (643-644), the subset (60i) is maintained (142) or returned (172) to full power operation until the interrupt (643-644) is finished (144, 174) and the repetitive operation resumes (644-642).

System power saving means and method

Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

Address lines load reduction

A system rapidly dynamic values (B) on a bus (12) to a programmable but thereafter fixed reference value (C). The system includes first leads (33) coupled to a comparison means (35), second leads (13) coupled to the bus (12) and third leads (34, 36) coupled to sources of potential (GND, VCC) related to logical HIGH and LOW of the fixed reference value (C). The leads (33, 13, 34, 36) are coupled in one or more programmable connection cell (32). Connections (471) or disconnections (461) are made between the leads (33, 13, 34, 36) so that the dynamic values (B) and the appropriate logical HIGH and logical LOW values are presented to the correct inputs of the comparison means (35). The programmable connections cells (32) invert the reference value (C) to (C) for coupling to the comparator (35). The system replaces a level of conventional decode logic (16) by the programmable interconnections (47), thereby reducing delay time, using fewer devices and occupying less circuit area.

High speed comparator with programmable reference

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Jerusalem, Israel

Eitan Zmora