Marvell Israel (misl) Ltd.

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

Marvell Semiconductor Israel Ltd.

Habana Labs Ltd.

Marvell International Limited

Eitan Joshua

Shaul Chapman

Noam Mizrahi

Yosef Solt

Erez Amit

Adi Habusha

Sujat Jamil

Gil Stoler

Scott Furey

Frank O'Bleness

Dimitry Melts

Moshe Raz

Amit Shmilovich

Itay Peled

Dan Ilan

Michael Weiner

Hunglin Hsu

Oren Shafrir

Chia-Hung Chien

Moshe Anschel

Tawfik Bayouk

Ofer Eizenberg

Ehud Eliaz

Yori Teichman

Bharat Kumar Daga

Ravi Krishnan Venkatesan

Husam Khshaiboun

A cache allocation module may facilitate dynamic cache allocation in an AI accelerator based on data access patterns. For instance, the cache allocation module may dynamically partition the overall cache in the AI accelerator into one or more processor-side caches and one or more memory-side caches. A cache line may start as being private and may be installed in a processor-side cache. The cache allocation module may dynamically change private cache lines to shared cache lines, e.g., by moving private cache lines from a processor-side cache to a memory-side cache. A private cache line can be read by one compute engine in the AI accelerator, versus a shared cache line may be read by multiple compute engines in the AI processor. After a cache line is moved from a processor-side cache to a memory-side cache, the cache allocation module may invalidate the cache line in the processor-side cache.

Dynamic cache allocation in artificial intelligence accelerator

An example cache memory includes a schedule module, control modules, a datapath, and an output module. The cache memory receives requests to read and/or write cache lines. The schedule module maintains a queue of the requests. The schedule module may assign the requests to the control modules based on the queue. A control module, which receives a request, controls the datapath to execute the request, i.e., to read or write the cache line. The control module can control the execution by the datapath from start to end. Multiple control modules may control parallel executions by the datapath. The output module outputs, e.g., to a processor, responses of the cache memory to the requests after the executions. A response may include a cache line. The cache memory may include a buffer that temporarily stores cache lines before the output to avoid deadlock in the datapath during the parallel executions of requests.

Cache memory with decoupled control paths

Embodiments described herein provide a method for accessing a host memory through non-volatile memory over fabric bridging with direct target access. A first memory access command encapsulated in a first network packet is received at a memory interface unit and from a remote direct memory access (RDMA) interface and via a network fabric. The first memory access command is compliant with a first non-volatile memory interface protocol and the first network packet is compliant with a second non-volatile memory interface protocol. The first network packet is unwrapped to obtain the first memory access command. The first memory access command is stored in a work queue using address bits of the work queue as a pre-set index of the first memory access command. The first memory access command is sent from the work queue based on the pre-set index to activate a first target storage device.

Methods and systems for accessing host memory through non-volatile memory over fabric bridging with direct target access

Systems and methods described herein provide for communicating an addressable request from cache circuitry to a cache memory. The addressable request is received at a hardware bridge coupled to the cache circuitry and is directed to the cache memory, wherein the cache memory includes a direct memory access (DMA) memory and a programmable input/output (PIO) memory operable within a same address space of the cache circuitry. A service command associated with the addressable request is sent from the hardware bridge to a microcontroller. In response to receiving the service command, the microcontroller activates the PIO memory by: 1) transferring write data from an on-die memory to the PIO memory when the service command is a write command, and 2) transferring read data from the PIO memory to the on-die memory when the service command is a read command.

Systems and methods for communicating addressable requests to a programmable input/output memory over a hardware bridge

In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Interconnected ring network in a multi-processor system

Embodiments include a network device comprising: at least one processing core; a packet processing module configured to perform a first set of packet processing operations at a first rate, to partially process data units that are received at the network device, the packet processing module being further configured to transmit ones of the data units to the at least one processing core, the at least one processing core being configured to perform a second set of processing operations at a second rate, wherein the second set of processing operations is different from the first set of processing operations; an interconnecting module configured to interconnect the packet processing module and the at least one processing core; and a rate limiter configured to selectively control a transmission rate at which the data units are transmitted by the packet processing module to the at least one processing core based on the second rate.

Method and apparatus for controlling a rate of transmitting data units to a processing core

Some of the embodiments of the present disclosure provide a multi-core processing system configured to selectively enter a dormant mode, comprising: a plurality of processing cores; a plurality of cache memories, wherein a cache memory is associated with one or more corresponding processing cores; and a coherency fabric configured to transmit snoop commands to the respective caches to maintain data coherency in data stored in the respective caches, the coherency fabric comprising: a queue configured to intercept and store snoop commands that are directed to a first cache when a first processing core associated with the first cache is in the dormant mode.

Multi-core processing system having cache coherency in dormant mode

Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.

Shared op-symmetric update-sensitive variables

Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.

Simultaneous eviction and cleaning operations in a cache

Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Synchronous multi-clock protocol converter

A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address in the cache memory, the cache memory divided into a plurality of banks. The method further includes determining a candidate address in each of the cache memory banks using an address determination algorithm, selecting one of the candidate addresses from among the determined candidate addresses using an address selection function different from the address determination algorithm, and returning the selected candidate address in response to the request.

Methods and systems for determining a cache address

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Ramot Menashe, Israel

Eitan Joshua