Marvell Israel (misl) Ltd.

Intel Corporation

Marvell Semiconductor Israel Ltd.

Marvell Asia Pte., Ltd.

Marvell International Limited

Marvell Israel (m.l.s.l) Ltd.

Marvel Semiconductor Israel Ltd.

Eitan E Rosen

Oded Norman

Thomas D Fletcher

Dan Lieberman

Javed Sabir Barkatullah

Jack Doweck

Lev Epstein

Tsafrir Israeli

Yakov Milstain

Shekhar Patwardhan

Rommel O Dizon

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

Method and apparatus for controlling clock cycle time

Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.

Method and apparatus for synchronization

Aspects of the disclosure provide an integrated circuit and method for varying a frequency of a clock signal to accommodate critical paths in the integrated circuit. The integrated circuit can include a clock generator configured to generate a clock signal having a clock frequency that is variable, circuitry that includes a plurality of critical modules that can be selectively activated to operate under control of the clock signal, each critical module including one or more critical paths that a default clock frequency cannot accommodate, and a controller that causes the clock generator to vary the clock frequency of the clock signal based on propagation delays of those critical paths in activated critical modules.

Critical paths accommodation with frequency variable clock generator

Aspects of the disclosure include an integrated circuit that includes a first circuit, a first performance detector, and a first regulator. The first circuit is configured to receive a first regulated voltage from a first voltage supply line disposed on the integrated circuit. The first performance detector includes a first speed monitor disposed adjacent to the first circuit, and the first performance detector is configured to generate a first control signal based on a first speed detection result from the first speed monitor. The first speed detection result corresponds to measuring an operational speed of the first circuit. The first regulator is configured to receive a global supply voltage from a power rail and output the first regulated voltage based on the global supply voltage and the first control signal.

Integrated circuit having regulator controlled based on operational speed

Aspects of the disclosure provide a system. The system includes a first functional circuit, a first clock generator, a second functional circuit, and a second clock generator. The first functional circuit is configured to be operative in response to a first clock signal. The first clock generator is configured to generate the first clock signal with a first clock cycle being a function of a first number of first inversion delays. The second functional circuit is configured to be operative in response to a second clock signal. The second clock generator is configured to generate the second clock signal with a second clock cycle being a function of a second number of second inversion delays. In an embodiment, the first inversion delays are correlated to switching delays in the first functional circuit, and the second inversion delays are correlated to switching delays in the second functional circuit.

Method and apparatus for gals system

An integrated circuit includes a circuit including a plurality of functional blocks, a sensor associated with one of the plurality of functional blocks for sensing a state of activity thereof, and a sleep switch receiving an output from the sensor and placing the associated functional block in a sleep state in response to the sensed state of activity.

Method and apparatus for activating sleep mode

Some of the embodiments of the present disclosure provide a method comprising outputting data at a logic circuit; and in anticipation of a possible change in the data during a data window, applying at least a partial inversion to an output of the logic circuit from a start of the data window.

Increasing switching speed of logic circuits

Aspects of the disclosure provide a clock generator circuit that includes a first pulse generator and a second pulse generator cross-coupled together. The first pulse generator is configured to output first pulses. Each first pulse has a first leading edge, a first trailing edge, and a first pulse width corresponding to a first delay time that is based on a first number of inversions. The second pulse generator is configured to output second pulses. Each second pulse has a second leading edge, a second trailing edge, and a second pulse width corresponding to a second delay time that is based on a second number of inversions. The first pulse generator outputs one of the first pulses in response to the second trailing edge, and the second pulse generator outputs one of the second pulses in response to the first trailing edge.

Method and apparatus for clock generator

Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit includes a multiplexer and a logic module coupled to the multiplexer. The multiplexer is configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. The logic module includes at least one of an XNOR and an XOR module and is configured to provide an output signal that is responsive to performing at least one of an XNOR and an XOR operation of the output of the multiplexer and an enable signal that enables or disables the clock gate circuit to generate the clock signal.

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Abrim, Israel

Eitan E Rosen