Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Eisuke Suekawa

Yoichiro Tarui

Masaaki Ikegami

Naoto Kaguchi

Yasunori Oritsuki

Naruhisa Miura

Shiro Hino

Masayuki Imaizumi

Katsumi Satoh

Tetsujiro Tsunoda

Naoki Yutani

Yasushi Takaki

Chihiro Tadokoro

Kazushige Matsuo

Kouichi Mochizuki

Shunsuke Sakamoto

Polysilicon films (P,P) are simultaneously formed on a wafer (W) and a monitor wafer (W) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P) formed on the monitor wafer (W) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P) formed on the wafer (W) is etched using the selected mask pattern to form the polysilicon resistor ().

Manufacturing method for a semiconductor device including a polysilicon resistor

The present technique relates to a semiconductor device including a current sensor, which can improve the electrostatic discharge ruggedness. The semiconductor device includes: a first switching element through which a main current flows; and a second switching element through which a sense current flows. The first switching element includes a first gate oxide film formed in contact with a first base layer sandwiched between a first source layer and a drift layer. The second switching element includes a second gate oxide film formed in contact with a second base layer sandwiched between a second source layer and the drift layer. A part of the second gate oxide film including a portion covering the second base layer is thicker than the first gate oxide film.

Semiconductor device

A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n-source region formed in an upper portion of an n-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

A semiconductor device includes a first MOS transistor and a second MOS transistor of a second conductivity type. The first MOS transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential. The second MOS transistor includes a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential. The control electrodes of the first and second MOS transistors are connected in common. The first and second MOS transistors are formed on a common wide bandgap semiconductor substrate. In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide bandgap semiconductor substrate. In the second MOS transistor, a main current flows in a direction parallel to the main surface of the wide bandgap semiconductor substrate.

The present invention includes a second source layer formed on a surface layer of a p base layer in the same step as that of forming a nsource layer to sandwich a field insulating film, a second gate electrode being the same layer as a gate polysilicon and formed at least on the field insulating film, a third gate electrode formed on one of portions of the second source layer to be electrically connected to the second gate electrode, and a second source electrode formed on the other portion of the second source layer.

Wide band gap semiconductor device

It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.

Silicon carbide semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate of a first conductivity type, including a first main surface and a second main surface opposite to each other. A power semiconductor element includes a first electrode in a first region at the first main surface of the semiconductor substrate, and a second electrode at the second main surface. A current flows between the first electrode and the second electrode. The semiconductor device also includes a guard ring of a second conductivity type, in a second region at the first main surface, at a more outer circumference than the first region. A semi-insulating insulation film covers the second region. A dielectric film in the second region covers the semi-insulating insulation film. A flow block portion in a third region at the first main surface, at a more outer circumference than the second region, prevents a flow out of the dielectric film.

A power semiconductor having a first, second, third, and fourth semiconductor layer on top of each other, two trench gates parallel and adjacent to each other, each having a trench in the fourth semiconductor layer with the a trench bottom portion reaching into the third semiconductor layer, a gate insulation film lining the trench, and a gate electrode filling the trench being lined with the gate insulation film, two first semiconductor region regions provided contiguously bordering on one side of each of the two trench gates, located at the outer sides of each of the two adjacent trench gates, and located in the top side of the fourth semiconductor layer, a first main electrode on the fourth semiconductor layer, and a second main electrode provided on a bottom of the first semiconductor layer.

Power semiconductor device

A semiconductor device includes a semiconductor layer including a base region of a second conductive type formed in a first surface of the semiconductor layer, an emitter region of the first conductive type formed in the base region, a buffer layer of the first conductive type formed on a second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity of approximately 5 &#xd7;10cmor less, and the collector layer has a maximal concentration of the second conductive type impurity of approximately 1&#xd7;10cmor more. The ratio of the maximal concentration of the collector layer to that of the buffer layer is greater than 100. The collector layer has a thickness of approximately 1 &#x3bc;m or more.

Semiconductor device having insulated gate bipolar transistor

A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate.

Insulated gate transistor

One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region of the first conductive type formed in the base region. Also, the semiconductor device includes a buffer layer of the first conductive type formed on the second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity therein of approximately 5&#xd7;10cmor less, and the collector layer has a maximal concentration of the second conductive type impurity therein of approximately 1&#xd7;10cmor more. Further, the ratio of the maximal concentration of the collector layer to the maximal concentration of the buffer layer being greater than 100. The collector layer has a thickness of approximately 1 &#x3bc;m or less.

An IGBT includes a plurality of ndoped regions () selectively formed in a main surface () of a psemiconductor layer () opposite from an n type semiconductor layer () without being connected to the n type semiconductor layer (). The ndoped regions () are formed in corresponding relation to and only under channel regions (CH-CH) of structures (-), respectively. This lowers the effective concentration of the psemiconductor layer () on the ndoped regions () to reduce the number of holes injected from a collector layer () in an off state, reducing a leakage current.

Insulated gate bipolar transistor

A semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer containing a p-type impurity in a relatively high concentration is provided as an operation region of a diode in one of main surfaces of a silicon substrate containing an n-type impurity in a relatively low concentration and a plurality of ring-shaped Schottky metal layers are concentrically provided on the main surface of the silicon substrate around the p-type impurity layer with a space formed therebetween to surround the p-type impurity layer. A silicon oxide film is provided on the main surface of the silicon substrate around the p-type impurity layer and an anode electrode is provided on the p-type impurity layer.

Growing community of inventors

Tokyo, Japan

Eisuke Suekawa