Kabushiki Kaisha Toshiba

Eishirou Take

Osamu Matsumoto

Kenjiro Kanayama

Tadashi Yabuta

A spare decoder has a first register, a second register, and a multiplexer for selecting the output of the first register or that of the second register. The first register stores data of a fuse element. In the ordinary operating mode, a defective memory cell is replaced by a spare cell in accordance with the data stored in the first register. In the test mode, it is determined whether at least one spare cell is defective or not. If there are no defective spare cells, the data that should be stored in the defective memory cell is written into one of the spare cells. Further, the address of the defective memory cell is written into the second register. The defective memory cell is replaced by one of the spare cells in accordance with the data stored in the second register, by cutting the fuse element in accordance with the address of the defective memory cell.

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Yokohama, Japan

Eishirou Take