Fuji Xerox Co., Ltd.

Eiri Hashimoto

Nobuaki Miyakawa

Hitoshi Ikeda

Taro Yokose

Yutaka Koshi

Kenichi Kawauchi

Tetsuro Kawata

Shinjiro Toyoda

Koumei Tomida

The present invention provides a variable-length code decoder for inputting a code data bit string having a predetermined number of code data bits in every decoding cycle and decoding it, which comprises storing means for storing a decoded symbol and a node in a code tree in the next decoding cycle corresponding to each combination of a value of the code data bit string and a node in the code tree, reading means for reading the decoded symbol and the node in the code tree in the next decoding cycle from the storing means in accordance with the code data bit string inputted in a current decoding cycle and the node in the code tree in the current decoding cycle, outputting means for outputting the decoded symbol read by the reading means, and providing means for providing the node in the code tree in the next decoding cycle read by the reading means to the reading means.

Variable-length code decoder

A variable-length code decoder includes plural barrel shifters, each of which executes shift processing on inputted variable-length code data bit by bit from the 0 bit to (the bit number of a maximum length codeword -1). The barrel shifters, which are in number equal to the bit number of the maximum length codeword, are arranged in parallel connection. Plural storing devices are provided, each of which stores a pair of a decoded symbol and codeword length thereof corresponding to code data. Plural fetching devices are provided, each of which fetches the pair of the decoded symbol and the codeword length thereof in accordance with the code data outputted from each of the barrel shifters. Each of the fetching devices is connected to a respective barrel shifter and storing devices. A selecting device is provided for selecting a predetermined pair from plural pairs of the decoded symbol and the codeword length fetched by the plural fetching devices in an initial decoding process. The selecting device further selects any one pair from the plural pairs of the decoded symbol and the codeword length utilizing the codeword length selected in the initial decoding process in subsequent decoding processes.

A proximal particle list including numbers of particles located within a predetermined distance from a particular particle is generated in calculating a Coulomb force acting on a particular particle or a related potential. A van der Waals force acting on the particular particle or a related potential is thereafter calculated based on only the particles included in the proximal particle list.

Computing method and apparatus for a many-body problem

A device for calculating differences includes a difference circuit for generating difference signals .DELTA.x.sub.j =x.sub.j -x.sub.i, .DELTA.y.sub.j =y.sub.j -y.sub.i, and .DELTA.z.sub.j =z.sub.j -z.sub.i between coordinates of i having (x.sub.i, y.sub.i, z.sub.i) coordinate signals and coordinates of j having (x.sub.j, y.sub.j, z.sub.j) coordinate signals in an orthogonal coordinate system. The difference circuit includes an x-axis circuit, responsive to the x.sub.i and x.sub.j signals having a first circuit for receiving the x.sub.i coordinate signal and the x.sub.j coordinate signal and generating the .DELTA.x.sub.j ; a comparison circuit for comparing the x.sub.i and x.sub.j signals and determining whether the .DELTA.x.sub.j is less than a first set value -L.sub.x /2 corresponding to a length of a side of a virtual rectangular parallelepiped or greater than a second set value L.sub.x /2 corresponding to the length of the side of the virtual rectangular parallelepiped, L.sub.x being a value indicating the length of an elongated side in the x-axis direction of the virtual rectangular parallelepiped; an adder circuit for receiving the L.sub.x and .DELTA.x.sub.j and adding the L.sub.x to .DELTA.x.sub.j when .DELTA.x.sub.j is less than -L.sub.x /2; and a subtraction circuit for receiving the L.sub.x and .DELTA.x.sub.j and subtracting L.sub.x from .DELTA.x.sub.j when .DELTA.x.sub.j is greater than L.sub.x /2. The difference circuit includes y-axis and z-axis circuits similar to the x-axis circuit.

Coordinate difference calculating device

A digital filter processing device includes at least a plurality of multipliers each for multiplying data signal by coefficient data, and an adder for adding together the multiplication results derived from the multipliers. The digital filter processing device further includes coefficient registers each for storing the coefficient data as is shifted so that a first effective digit of the coefficient data lies at the left end, shift-quantity registers provided in connection with the coefficient registers, and each for storing a quantity of shift equal to the shift quantity of the coefficient data, and barrel shifters each for shifting the digits of an output data from each of the multipliers by the shift quantity stored in each of the shift-quantity registers, in the opposite direction to that of the shift in each of the coefficient registers. The digital filter processing device may further include a second shift-quantity register for storing a second quantity of shift, and a second barrel shifter for shifting the digits of the output data of the adder by the second shift quantity.

Digital filter processing device

An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.

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Kanagawa, Japan

Eiri Hashimoto