Sun Microsystems, Inc.

Eileen H You

Matthew E Becker

Weize Xie

Peter Redmond O'Brien

John F MacDonald

Micah C Knapp

Thomas E Dillinger

Daniel J Flees

Chung Lau Chan

In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

Timing analysis of latch-controlled digital circuits with detailed clock skew analysis

A method and a system for static timing analysis of a latch-based circuit. A netlist data structure represents the latch-based circuit. The method statically analyzes the netlist data structure and produces timing information for signal paths within the latch-based circuit. The signal paths are filtered using path termination information, which specifies where paths end. The path termination information distinguishes a first signal path that terminates at a latch from a second signal path that flows through that same latch.

Path filtering for latch-based systems

A method for extracting parasitic capacitance from an integrated circuit layout includes decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions. The method further includes summing capacitances between the conductive segments in a selected net and the other conductive segments in the integrated circuit layout that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value. The method further includes summing capacitances between the conductive segments in the selected net and the other conductive segments in the integrated circuit layout that are transverse to the conductive segments in the selected net to obtain a second capacitance value. The first capacitance value and the second capacitance value are added together to obtain a total capacitance value for the selected net.

Hierarchical parasitic capacitance extraction for ultra large scale integrated circuits

A technique measuring accuracy of parasitic capacitance extraction defines the error in an extracted total net parasitic capacitance intended for timing analysis as a sum of the errors in the extracted values of the individual capacitance elements, with the error for each element being influenced by a weight factor. Similarly, the technique defines an error in the extracted value of a crosstalk factor for the net of interest as a difference between the errors in the extracted values of the individual capacitance elements, with the error in each element being influenced by a weight factor. For signal timing and crosstalk analyses, the weight factors allow a designer to focus calibration of the extraction tool on the capacitive element having the highest weight factor.

Growing community of inventors

Saratoga, CA, United States of America

Eileen H You