Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Eiki Kondoh

Takao Yaginuma

Atsushi Hasegawa

Shigeki Morinaga

Ikuya Kawasaki

Shigeo Kuboki

Kazuhiko Iwasaki

Norihiko Sugimoto

Tsuneo Funabashi

Masahiro Ueno

Tomoaki Aoki

Takeshi Asai

Shunji Inada

Hideo Inayoshi

Toshihiko Tominaga

Kazuhisa Inada

In a data communication adapter apparatus for a digital data communication connected between a signal transmission path for transmitting both receive data and transmit data, and a host processor unit for producing frame data to output the frame data therefrom, an internal host bus is newly employed in the data communication apparatus irrelevant to the employment of a CPU dedicated bus, and the transmission/reception data generated and interpreted by the host processor is transferred via the internal host bus, a bus interface, and a system data bus between a transmission memory or a reception memory and a buffer memory. Furthermore, a reception memory (host dedicated reception memory) for storing only the reception data to be interpreted by the host processor is separately provided with another reception memory (CPU dedicated reception memory) for storing only the reception data to be interpreted by a CPU, one reception data to be interpreted by the CPU is once transferred from the transmission/reception control unit to the CPU dedicated memory and thereafter read out via the CPU dedicated bus under the control of the CPU, and the other reception data to be interpreted by the host processor is one stored in the host dedicated reception memory and then read out via the internal host bus and bus interface under the control of the host processor.

Data communication adapter and data communication terminal apparatus for

When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal (CYCYCL) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the CYCYCL signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle. Thus, the signal transfer between memory and coprocessor can be completed within one bus cycle without resort to the provision of duplicate hardware in the coprocessor.

Data processing system with coprocessor

A function arithmetic unit which performs elementary operations at high speeds and which enables required memory capacity to be reduced. The function arithmetic unit includes a constant memory which stores a constant that corresponds to the number of successive iterative operations; a controller which causes addition or subtraction in the successive iterative operations; and arithmetic units which receive, as initial values, an argument of an elementary function value to be found and two constants determined depending upon the elementary functions to be found, and which subject these initial values to n iterative operations to produce elementary function values. A further arithmetic unit subjects the elementary function values to multiplication, addition, subtraction, or division, or a combination thereof, thereby to produce the thus obtained value.

Elementary function arithmetic unit

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Hitachi, Japan

Eiki Kondoh