Hitachi, Ltd.

Hitachi Microcomputer Eng. Ltd.

Hitachi Information Technology Co., Ltd.

Hitachi, Vlsi Eng. Corp.

Eiki Kamada

Tohru Shonai

Yooichi Shintani

Kiyoshi Inoue

Kazunori Kuriyama

Shigeo Takeuchi

Motohisa Ito

Tatsumi Yamauchi

Hiromichi Yamada

Fumio Murabayashi

Akira Nishimoto

Naonobu Sukegawa

Akira Yamaoka

Yoshikazu Kiyoshige

Noriyasu Ido

Satoshi Oguni

Masakazu Fukagawa

Shigeko Hashimoto

Kei Yamamoto

Takahiro Nishiyama

Toshiko Isobe

Kouki Uwano

Katsutoshi Uehara

Akira Hirono

A cache memory system employing a set associative system with a plurality of ways which can store data having a same set address is disclosed. The cache memory system includes a replace circuit for controlling replacement of data stored in a cache memory according to a predetermined replace algorithm, and a limiting circuit for limiting ways to which blocks to be replaced by the replace circuit belong. The limiting circuit receives a mode signal specifying whether replace ways should be limited. The limiting circuit limits ways to be replaced when the mode signal indicates that the limitation should be performed and an instruction to be executed is a prefetch instruction.

Cache memory system having a replace way limitation circuit and a processor

A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.

Multiprocessor synchronization and coherency control system

A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

Floating-point arithmetic processing apparatus

An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.

Information processing system and information processing method for

A store buffer apparatus connected to a CPU and a main storage unit includes a first buffer for holding a pair of store address and store data in the main storage unit supplied from an operation execution unit of the CPU, a first latch connected to the first buffer means for holding the store address, a second latch connected to the first latch for holding an output of the first latch, a judgment device for comparing an output read out from the address array with an output of the second latch to thereby judge whether the cache hit check for the store address is successful or not and a second buffer for holding the pair of store data and store address having successful cache hit check judged by the judgment device. Occurrence of the state that the store buffer is full is reduced. Two data stored in the second buffer can possess a format into which the two data can be merged.

Store buffer apparatus with two store buffers to increase throughput of

An information processing apparatus based on a VLIW system which eliminates an idle execution part generated during execution and which uses execution parts efficiently to obtain a high parallel processing ability of instruction execution. The information processing apparatus simultaneously executes m of multiple threads of long instructions each made up of n of operational instructions. When it is desired to process 3 threads with 4 of the operational instructions as an example, the information processing apparatus includes 3 instruction decoders corresponding to the 3 threads, 4 instruction schedulers for the operational instructions, and 4 execution parts corresponding to the 4 operational instructions. The instruction decoders, which are operated independently of each other, include a circuit for resolving a resource competition relationship and a data dependent relationship and a circuit for controlling instruction issuance. Thus, even when a previous instruction is being executed, the subsequent instructions are issued to the respective instruction schedulers respectively independently when there is no resource competition relation and also no data dependent relationship. Each of the instruction schedulers performs scheduling operation over the operational instructions to be sent to the corresponding execution parts between the plurality of threads.

Processing apparatus for executing a plurality of VLIW threads in

A memory array area of a semiconductor chip is divided into a plurality of partial memories. Each partial memory is provided with a register. The distance between adjacent registers is set shorter than a maximum distance which that data can travel in the memory in one data transfer cycle defined by a clock signal. These registers are serially connected and provides a path through which addresses, input data, and control signals are transferred to desired partial memories in synchronism with the clock signal. Output data and status signals are also transferred through these registers to a memory output terminal in synchronism with the clock signal.

Memory with sequential data transfer scheme

An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.

Information processor providing enhanced handling of address-conflicting

Data processor for concurrent executing of instructions by plural

A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.

Data processor for parallelly executing conflicting instructions

A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.

Pipelined data processor capable of decoding and executing plural

An information processing apparatus for executing instructions in parallel includes circuitry which, when a first instruction requesting reading of an operand from a certain address of the main storage or buffer storage has been decoded, detects among instructions in execution the presence of a second instruction requesting writing of an operand held by a register such as a general-purpose register into that address of the main storage without implementing an operation on the operand. If the second instruction has been detected, the invention reads out an operand from the register specified for operand reading by said second instruction before operand writing into the main storage by the second instruction is completed.

Information processing apparatus for determining sequence of parallel

A buffer or a plurality of buffers are provided each for holding a write address and an address specifying a write position which are obtained as a result of an execution based on a predicted result. The execution of the instruction is continued up to the operation stage regadless of whether or not the instruction is being executed in the predicted state, the data and the write address are held in the buffer written. The data in the buffer is canceled if the prediction is found to be wrong when the predicted state is completed, and the data is utilized if the prediction is found to be correct.

Data processor capable of executing instructions under prediction

In accordance with the invention, there are disposed a logical register group and a physical register group. Direct access is made to the logical register group on the basis of a register number designated by an instruction. To make access to the physical register group, there is disposed a circuit which converts the register number designated by the instruction to a physical register number. A plurality of arithmetical or logical operation units (ALUs) are disposed to execute a plurality of instructions in parallel. There is further disposed a circuit which supplies an operand data from the physical register group to each ALU and writes the operation result data of each ALU into the physical register group and into the logical register group. When a write register number designated by a preceding instruction A and a succeeding instruction B has the same value a, mutually different physical register numbers b' and b' are determined with respect to the write register number a for both instructions A and B. Therefore, the instruction B can be executed in parallel with the instruction A before the operation of the instruction A is complete.

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Hadano, Japan

Eiki Kamada