Forschungszentrum Juelich Gmbh

Rheinisch-westfaelische Technisque Hochschule (rwth) Aachen

Rheinisch-westfaelische Technische Hochschule Aachen (rwth)

Rheinish-westfaelische Technische Hochschule Aachen (rwth)

Eike Linn

Rainer M Waser

Ilia Valov

Roland Daniel Rosezin

Stefan Tappertzhofen

Lutz Nielen

Rainer Bruchhaus

Florian Lentz

Carsten Kuegeler

A method for reading out a non-volatile memory element having at least two stable states 0 and 1. This memory element comprises at least one resistive memory cell, which encodes the two states 0 and 1 into a state HRS having higher electrical resistance and a state LRS having lower electrical resistance. In the two states 0 and 1, the memory element has differing capacitances C; this difference is used to determine which state is present. A memory element is selected in which a fixed capacitance that is independent of the state of the memory cell is connected in series with the memory cell. A series connection of a resistive memory cell with a fixed capacitance, instead of with a second resistive memory cell, improves the signal strength during capacitive read-out. The second memory cell becomes indispensable for the memory function when the memory element is read out capacitively. Moreover memory elements were developed which combine a field effect transistor or a DRAM structure with a resistive memory cell or an antiserial series connection of such memory cells.

Method for capacitively reading resistive memory elements and nonvolatile, capacitively readable memory elements for implementing the method

A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.

Method for nondestructively reading resistive memory elements

Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V, it can be transferred into the likewise high-impedance state 1. By applying a read voltage V, the magnitude of which is smaller than the write voltages Vand V, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.

Memory element, stacking, memory matrix and method for operation

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Wuerselen, Germany

Eike Linn