Nuvoton Technology Corporation Japan

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Pegasus Sewing Machine Mfg. Co., Ltd.

Panasonic Semiconductor Solutions Co., Ltd.

Eiji Yasuda

Ryosuke Okawa

Kazuma Yoshida

Toshikazu Imai

Shigetoshi Sota

Takeshi Imamura

Yasuyuki Masumoto

Tadayoshi Nakatsuka

Hironao Nakamura

Masaaki Hirako

Ryou Kato

Yoshihiro Matsushima

Kenichi Hidaka

Atsushi Watanabe

Mitsuaki Sakamoto

Tomonari Oota

Katsushi Tara

Akira Kimura

Tsubasa Inoue

Takashi Kasuda

Minoru Nakano

Masahide Taguchi

Kazuo Noguchi

Shozo Hikiguchi

Michiya Otsuji

Yukihiro Nishimura

Tomonari Ota

Dohwan Ahn

A semiconductor device includes a vertical field-effect transistor including: a first gate trench and a second gate trench extending in a first direction, the second gate trench being deeper than the first trench; a first gate insulating film and a first gate conductor inside the first gate trench; and a second gate insulating film and a second gate conductor inside the second gate trench. The first gate conductor and the second gate conductor have the same potential. When a total number of first gate trenches is denoted by n, a total number of second gate trenches is at least 2 and at most n+1. In a second direction orthogonal to the first direction, the second gate trench is disposed at each of farthest ends of a region in which the first gate trenches and the second gate trenches are disposed.

Semiconductor device

A semiconductor device includes a vertical field-effect transistor including: a low-concentration impurity layer; a body region; a gate trench; a gate insulating film; and a gate conductor. The body region includes: a first body portion containing an active region and has a constant depth; and a second body portion adjacent to the first body portion and includes a zone that has a limited length in a second direction orthogonal to the first direction along the top surface of the low-concentration impurity layer, and has a constant depth at a position shallower than the constant depth of the first body portion. The second body portion includes a portion in which a region having relatively high concentration of an impurity and a region having relatively low concentration of an impurity are alternately and periodically present in the first direction in a cross-sectional view of a plane orthogonal to the second direction.

A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm&#x2264;Lxr&#x2264;0.20 &#x3bc;m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors. The thickness of the backside electrode ranges from 25 to 35 &#x3bc;m, and the ratio of the thickness of the backside electrode to the thickness of a semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is 0.32 or more.

Semiconductor device, semiconductor module, and packaged semiconductor device

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 &#x3bc;m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.

Semiconductor device including first and second metal oxide semiconductor transistors

When a low level voltage is inputted to an input terminal IN, a transistor EFenters a blocked state, a first switch circuit SWenters a conduction state, and a second switch circuit SWenters the blocked state. Accordingly, a boosted voltage outputted from a voltage booster circuit CP is applied to a load R. When a high level voltage is inputted to the input terminal IN, the transistor EFenters the conduction state, the first switch circuit SWenters the blocked state, and the second switch circuit SWenters the conduction state. Accordingly, a voltage equivalent to that at the external power supply terminal VDD is applied to the load R. Therefore, although a current constantly flows through the transistor EFwhen the boosted voltage is not required, such situation does not affect a current supplied from the voltage booster circuit CP.

Current control circuit used for voltage booster circuit

A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

High frequency switching circuit device

A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (Cand C, Cand C) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.

High-frequency switch circuit arrangement

The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of the gate electrode.

Field-effect transistor

A needle thread feed regulating device utilized in high speed overedge sewing machines which form safety stitches composed of overedge stitches and double chain stiches. The needle thread feed regulating device comprises a thread guide mounted on the sewing machine frame and an oscillating thread guide which moves in cooperation with the sewing machine main shaft. The oscillating thread guide has a cam plate which regulates the feed of both the thread for overedge stitches and the thread for double chain stitches.

Growing community of inventors

Osaka, Japan

Eiji Yasuda