Matsushita Electric Industrial Co., Ltd.

Canon Kabushiki Kaisha

Eiji Yamauchi

Hiroshi Tanaka

Tetsuo Ishiwata

Susumu Yamaguchi

Tadashi Yoshino

Hitoshi Komae

Kiyokazu Hashimoto

Tatsuro Juri

Shinichiro Uno

Takao Kashiro

Makoto Mitsuda

Shuzo Hitotsumachi

Iwao Hidaka

Yoshiki Yamamoto

Hidemi Oka

Tomoo Nakagawa

An operation of a recording/reproducing portion is controlled by a control portion so as to record data in a predetermined recording region on a recording medium, and perform update recording in the predetermined recording region in accordance with occurrence of update information of the data. The control portion further has a function of controlling the recording/reproducing portion so as to record an update portion of data in a temporary storage region in a part of the recording medium and record an update flag showing whether the predetermined recording region has been updated with the update portion or has not been updated with the update portion in an update flag region, and in update recording with respect to the predetermined recording medium, successively performs operations of recording the update portion in the temporary storage region, setting the update flag in a non-updated state, recording the update portion in the predetermined recording region, and setting the update flag in an updated state.

Information recording apparatus and method for recording information on recording medium

An encoder generating an analogue color signal is configured by a digital circuit. An external frame signal supplied from an external apparatus is counted by a clock pulse signal generated by a crystal oscillator, and a synchronizing signal to be added to the luminance signal is produced on the basis of a counted results, and all horizontal synchronizing periods of digital active lines are made identical, and in vertical blanking period, a predetermined horizontal synchronizing period is made variable.

Apparatus for producing a video signal in synchronism with an external

The digital processing apparatus includes a high speed response PLL that produces a first clock signal locked on the horizontal synchronization signal included in the video signal input thereto. An analog to digital converter converts the input video signal with respect to the first clock signal into a digitized video signal. A write controller controls a video memory to store the digitized video signal based on the first clock signal. A low speed response PLL produces a second clock signal based on the vertical synchronization signal included in the video signal. A read controller controls the video memory to read out the stored digitized video signal therefrom based on the second control signal. The digital processing apparatus can store and read the digitized video signal to and from the video memory stably, enabling the video signal read from the video memory to be processed effectively and securely.

Digital processing apparatus using two synchronization signals

In a recording apparatus for video signals, adjacent pixels in input image signals are collected as blocks and subjected to orthogonal transformation. Then, the dc component, control data, ac components, end-of-block signal and the like in a block after orthogonal transformation are coded and the codewords are arranged in prescribed record areas. One or a plurality of record areas forms a correction area, and error correction coding is performed and recorded on the data in a correction area. When record data are reproduced and recorded again, errors are detected in the unit of the error correction area. The dc component and the like in a record area wherein an error which cannot be corrected exists are replaced by a codeword which is not used ordinarily, and a codeword for the first ac component is replaced by an end-of-block codeword.

Video recording and reproducing apparatus

There is provided a signal processing system for recording and reproducing a video signal and a digital audio signal with a rotary-head VTR and, more particularly, a memory control system which generates a block address and a memory write signal so that the sync signal for reproduced digital data is detected reliably and the digital data is stored in the memory circuit correctly.

Sync signal detection system in a memory system for recording and

A phase locked loop is disclosed in which a digital audio signal is recorded in synchronism with a video signal and a sampling frequency of the digital audio signal is reproduced in reproduction mode. A frequency divider of the phase locked loop comprising a phase comparator a low-pass filter, a VCO and a frequency divider unit is switched by the number of the digital audio signal recorded for each vertical sync period (or 1/N thereof) of the video signal, so that a sampling frequency of the digital audio signal having no relationship of integral ratio with a vertical sync frequency Fv of the video signal is reproduced from the same frequency Fv. The reference input to the phase comparator is delayed by a predetermined time in accordance with the number of the digital audio signal, with the result that the sampling frequency reproduced has no period error to the extent that the reference input has no period error.

Sampling frequency reproduction system

A signal processing system for absorbing asynchronism between a video signal and an audio signal which is caused when a PCM audio signal is to be recorded together with the video signal on a helical scan-type tape recorder. When the video signal and the audio signal are recorded on the same track, a recording band width of the audio signal should be narrow. A sample pattern is provided which assures rapid pull-in for both data clock reproduction and carrier reproduction, when the audio signal is modulated by QPSK or when Q-QPSK modulation is used.

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Katano, Japan

Eiji Yamauchi