Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Eiji Takeda

Tokuo Kure

Toru Kaga

Yoshio Sakai

Naotaka Hashimoto

ShinIchiro Kimura

Yoshifumi Kawamoto

Shinichiro Kimura

Digh Hisamoto

Katsuhiro Shimohigashi

Atsushi Hiraiwa

Takashi Nishida

Dai Hisamoto

Takashi Hashimoto

Toshiaki Yamanaka

Masahiro Moniwa

Shimpei Iijima

Haruhiko Tanaka

Koichiro Ishibashi

Katsutaka Kimura

Shoji Shukuri

Hideyuki Matsuoka

Akihiro Shimizu

Toshiaki Masuhara

Yoshiaki Kamigaki

Osamu Minato

Hideo Sunami

Hiroo Masuda

Kazuhiko Sagara

Toshiyuki Yoshimura

Yasuo Igura

Kiyoo Itoh

Shuji Ikeda

Toshihiko Tanaka

Norio Hasegawa

Yoshinobu Nakagome

Ryoichi Hori

Satoshi Meguro

Natsuki Yokoyama

Hiromasa Noda

Tsuneo Terasawa

Shinichi Minami

Yoshimune Hagiwara

Kazunori Tsujimoto

Nobuyuki Moriwaki

Kazuyoshi Torii

Norio Saitou

Katsuro Sasaki

Kozo Mochiji

Takashi Soga

Shoji Hanamura

Soichi Katagiri

Minoru Hidaka

Taro Ogawa

Shin'ichiro Kimura

Eiichi Seya

Yasuhiro Sugawara

Hiroaki Oizumi

Shigeru Honjo

Ryuichi Izawa

Masaaki Ito

Akemi Hamada

Toru Koga

Shuji Shukuri

Massaaki Ito

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

Semiconductor memory device

Semiconductor memory device having stacked capacitors

An optical element which allows replication of a refined pattern and a projection exposure apparatus employing the optical element are disposed so that side face portions of predetermined patterns which create shadows from oblique incident exposure radiation may be minimized at a predetermined incidence angle of vacuum ultrasonic radiation or X-radiation, or the patterns of the optical element are formed such that the direction in which incident radiation is reflected regularly and the direction of side faces of the patterns may extend in parallel to each other. When the optical element is irradiated to replicate or image the patterns of the optical element, refined patterns can be replicated or imaged.

Optical element and projection exposure apparatus employing the same

A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

Method of manufacturing a semiconductor device having silicon islands

A technique and exposure apparatus measures, with a high degree of accuracy, figure and placement errors of individual optical elements constituting optics embedded inside of an exposure apparatus or the like, with the optics kept in an embedded state as they are. The system measures the distribution of wavefront distortions in the optics while changing the positions of a light source and an image point inside an exposure field of the optics being observed. Optimal displacements of reflective surfaces constituting the optics are then found by calculation based on the measured distribution of wave-front distortions. Finally, the positions of the reflective surfaces are corrected in accordance with the calculated optimal displacements. The positions of the reflective surfaces are corrected by individually controlling displacements output by a plurality of actuators attached to each reflective surface and by mechanically modifying appropriate portions of the reflective surfaces.

Methods for measuring optical system, and method and apparatus for

Method of fabricating stacked capacitor cell memory devices

Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench. Also disclosed is a method of operating the memory cell, wherein the voltage applied to the word line, in a standby condition, is intermediate to the voltage applied to the word line during the writing operation and during the reading operation.

Semiconductor memory having writing and reading transistors, method of

A semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size. The semiconductor memory device employs memory cell charge holding electrode that is insulated from the remaining memory cell structure, particularly the switching transistor source drain leakage path. The write element controls the tunneling of charge carriers through such insulator to the charge holding portion or capacitor electrode, for writing data. Particularly, the write element includes a PN junction for various advantages.

Capacitive memory having a PN junction writing and tunneling through an

An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

Method for manufacturing a semiconductor device and a semiconductor

There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.

Semiconductor memory device having static random access memory

A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.

Process for fabricating field effect transistor

The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

Semiconductor device having a low-resistivity planar wiring structure

A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.

Dynamic random access memory having trench capacitors and vertical

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

Semiconductor memory device having stacked capacitor cells

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Koganei, Japan

Eiji Takeda