Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Ulsi Engineering Corp.

Renesas Technology Corp.

Eiji Sakakibara

Mitsuru Watabe

Yasushi Akao

Kouki Noguchi

Shumpei Kawasaki

Shigeki Masumura

Kaoru Fukada

Shiro Baba

Keiichi Kurakazu

Takanaga Yamazaki

Toshimasa Kihara

Takashi Tsukamoto

Yugo Kashiwagi

Masahiro Kainaga

Katsuhiko Ishida

Yoichi Asano

Shuya Fujita

Yasuhiro Tawara

Noriko Sawa

Hideaki Chaki

Tadahiko Sugawara

Kiyoshi Matsubara

Kazufumi Suzukawa

Isamu Mochizuki

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Microcomputer and dividing circuit

A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Branch instruction having different field lengths for unconditional and conditional displacements

Microcomputer having variable bit width area for displacement

Central processing unit having instruction queue of 32-bit length

Microcomputer having variable bit width area for displacement and

A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

Microcomputer and microcomputer system

A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.

Division circuit and the division method thereof

Multiply connectable microprocessor and microprocessor system

Microcomputer having 16 bit fixed length instruction format

Growing community of inventors

Kodaira, Japan

Eiji Sakakibara