Kabushiki Kaisha Toshiba

Eiji Sakagami

Masahisa Sonoda

Hiroaki Tsunoda

Keisuke Yonehama

Kazuhito Narita

Hideyuki Kobayashi

Makoto Nakashima

Seiichi Mori

Tadashi Iguchi

Kiyomi Naruke

Takanori Matsumoto

Naoki Koido

Kenji Matsuzaki

Hidemi Kanetaka

Hiromasa Fujimoto

A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer.

Semiconductor memory device and method of manufacturing the same

The semiconductor device of the present invention includes a semiconductor substrate, a plurality of floating gate electrodes formed in a memory cell forming region of the semiconductor substrate, a word line electrically connecting the floating gate electrodes and a conductor portion formed on the word line so as to reduce a resistance of the word line.

Semiconductor device

A nonvolatile semiconductor memory device includes floating gates, source areas, drain areas, word lines, diffusion layers, source lines and shield wires. The source area is shared by the floating gates adjacent to each other in a column direction. The drain area faces the source area in the column direction with the floating gate. The drain area is wider than the source area in the column direction. The diffusion layer is formed on an inner wall of a trench made between the source areas adjacent to each other in the same row direction and electrically connects the adjacent source areas together. The source line is formed of the source area and diffusion layer on the same row. The shield wire is disposed on and along the source line. A top surface of the shield wire is lower than that of the floating gate adjacent to the shield wire.

Nonvolatile semiconductor memory device comprising shield electrode on source and method for manufacturing the same

A method of fabricating a semiconductor device, including: forming a first well of a second conduction type and a second well of a first conduction type on a semiconductor substrate of the first conduction type, forming a gate oxide corresponding to each element on a surface of the semiconductor substrate, forming trenches by etching at forming locations of first and second trench isolating regions respectively at a first depth larger than a depth of a diffusion layer formed in a memory-cell forming region within the second well and smaller than a depth of a diffusion layer of a transistor of a peripheral circuit region, executing additional etching at a forming location of the second trench isolating region so that a second depth larger than the first depth is obtained and doping the trenches at the forming locations of the first and second trench isolating regions respectively, with a doping agent, thereby executing a planarization process.

Semiconductor device and method of fabricating the same

Semiconductor device and method of manufacturing the same

A semiconductor device includes an element isolation insulating film adjacent to an active area, a gate insulating film formed on a semiconductor substrate in the active area, paired gate electrodes located on the gate insulating film, a contact plug located on the active area between the gate electrodes, a pair of first upper lines located on the gate electrodes, a second upper line located on the gate electrodes, and a stopper film above upper surfaces of the gate electrodes and side surfaces of the gate electrodes. The element isolation insulating film has a first height of an upper surface thereof with reference to an upper surface of the semiconductor substrate and a second height of another upper surface thereof with reference to another upper surface of the semiconductor substrate. The first height is smaller than the second height.

A method for manufacturing a semiconductor device includes forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, the gate insulating film and the semiconductor substrate to form a trench which is used to electrically isolate a device region for forming a device from the remainder region on the substrate top surface; and etching the inside of the trench using a gas containing Cland HBr with a different condition from the etching condition of the semiconductor substrate.

A semiconductor memory device, including a first memory cell having a first gate electrode, a first diffusion layer, and a second diffusion layer; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer.

Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof

A NOR type semiconductor storage comprising memory cells, word lines, local and main source lines of metal and bit lines is disclosed. Two adjacent cells on a column form one set and share the drain region. Two adjacent cell sets on a column share the source region. Cell columns are isolated by trench type element isolation regions. A local source line run on and is connected to the source regions of the cells on a row. The main source lines are arranged intermittently between the bit line columns and are connected to the local source lines. A height of embedded layers in the element isolation regions under the local source lines or a height of a portion of the embedded layers contacting the substrate is lower than an upper surface of the source regions under the local source lines. The local source lines are connected to the well region.

Nonvolatile semiconductor storage apparatus and method of manufacturing the same

In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device including forming a laminate structure which includes a gate insulation film on a semiconductor substrate and a gate electrode material film on the gate insulation film, processing the gate electrode material film to obtain a gate electrode having a reverse tapered cross section, and forming a device isolation insulation film in direct contact with a side surface of the gate electrode.

Method of manufacturing semiconductor device using STI technique

This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.

A nitride film (,A) as a had pattern mask in a peripheral transistor forming region and a cell transistor forming region is narrowed by A,into a narrower nitride film (,B) by pull-back. While the narrower oxide film (,B) in the cell transistor forming region is covered by an oxide film (,), the narrower nitride film (,B) in the peripheral transistor forming region is further narrowed by A,into a still narrower nitride film (,C) by pull-back. By making apertures (,A,,B) in a buried oxide film (,) by using the narrower nitride film (,B) and the still narrower nitride film (,C), STI edges made of the buried oxide film (,) can be prevented from depressing or falling down.

Manufacturing method of a semiconductor device and a nonvolatile semiconductor storage device

The present invention discloses a nonvolatile semiconductor memory device having a memory cell transistor in which an offset region is provided as a charge carrier injecting region. An insulating film and a gate electrode is formed in order of mention on a semiconductor substrate. Source/drain regions are formed on the surface of the semiconductor substrate with the gate electrode interposed therebetween. The drain has an LDD (Lightly Doped Drain) structure. Furthermore, a layered film of silicon oxide films and a SiN film is provided on a channel region between an edge of the gate electrode and a source diffusion layer. To be more specific, the layered film is formed in such a way that the SiN film is interposed between the silicon oxide films, constituting a side wall of the gate electrode. The SiN film is a charge carrier accumulating layer. Contact holes are formed in an insulating film between layers, respectively reaching the source and drain regions. Each of the contact holes are filled with a conductive material (contact plug). A conductive barrier film (diffusion protecting film) is provided on the bottom and to the inner wall portions of the contact hole. The contact plugs respectively connect the source and the drain to upper layer, aluminium wiring.

Nonvolatile semiconductor memory device having memory cell transistor

The invention provides a novel method of manufacturing a semiconductor device comprising those sequential steps including the following, formation of a floating gate electrode on a region predetermined for the formation of the first conductive channel across an insulation film, followed by superimposition of a control gate electrode on the floating gate electrode across another insulation film. After completing the formation of the stacked gate electrode unit, the first conductive impurities are injected into silicon substrate by applying a minimum of 8 degrees of angle against the normal of this substrate under aid of ionic injection, and then forms a region containing strong density of the first conductive impurities adjacent to the boundary of a layer of diffused second conductive impurities which is at least predetermined to become the drain region of the transistor incorporating the stacked gate electrode unit. As a result of the provision of the region containing strong density of impurities injected in the oblique direction, the efficiency in the writing of data into the floating gate electrode is significantly promoted, and at the same time occurrence of 'short-channel' effect can securely be suppressed as well.

Growing community of inventors

Yokkaichi, Japan

Eiji Sakagami