Fujitsu Corporation

Eiji Noguchi

Hiroshi Shimada

Keizo Aoyama

Hideo Itoh

Kenji Agatsuma

Keizoh Aoyama

A static memory circuit includes memory cells arranged in a matrix of word lines and bit lines, and a reset circuit for resetting each pair of bit lines to have an equivalent potential in response to a change in a row address signal. The reset circuit generates a reset signal at a first time a certain time period after a first change of the row address signal and terminates the reset signal at a second time when a second change of the row address signal is detected. Thus, data destruction during reading is prevented.

Static memory circuit

A decoder for decoding address signals and a clock signal, in a synchronous CMOS memory, comprising an MOS transistor of one conductivity-type, to whose gate is applied a clock-including address signal, and a plurality of MOS transistors of the opposite conductivity-type connected in series, to each gate of which is applied the address signal and the clock-including address signal, respectively, whereby a terminal connecting the MOS transistor of one conductivity-type and the MOS transistors of the opposite conductivity-type serves as an output.

Decoder

Disclosed is column decode circuit for a random access memory, which column decode circuit is comprised of a conventional transfer gate transistor, conventional driver transistors and a conventional load transistor. The column decode circuit further includes a chip enable gate transistor according to the present invention. The conventional gate transistor transfers data stored in a corresponding memory cell of the random access memory in accordance with a column address information. The column address information received by the conventional driver transistors connected in parallel causes the above gate transistor to be conductive or nonconductive. Accordingly, the conventional load transistor will apply a voltage of a particular voltage level (Vcc) from a voltage supply to the gate of the transfer gate transistor. The chip enable gate transistor, the load transistor and the parallely connected driver transistors are all connected in series. The thus connected column decode circuit has a very low power consumption and a high speed operating capability.

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Kawasaki, Japan

Eiji Noguchi