Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Eiji Miyagoshi

Akihiro Watabe

Hiroshi Takeno

Hiroshi Imanishi

Ryoji Yamaguchi

Toshihide Akiyama

Noboru Mizuguchi

Shintarou Nakatani

William Brent Wilson

Takayuki Morishige

Yoshiyuki Goi

A formatteris provided and, when a code sequence which matches a part ('00') of the head of a predetermined code sequence detected by a start code prefix detection unit, is detected, the start code prefix detection unitdetects the residual part ('00', &#x2018;00&#x2019;, &#x2018;01&#x2019;, &#x2018;E0&#x2019;) of the detected predetermined code sequence to detect a pattern of (&#x2018;00&#x2019;, &#x2018;00&#x2019;, &#x2018;00&#x2019;), and the formatteroutputs one (&#x2018;00&#x2019;). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer, data corresponding to code sequences other than the code sequence (&#x2018;00&#x2019;, &#x2018;00&#x2019;, &#x2018;01&#x2019;, &#x2018;E0&#x2019;) indicating the packet boundary are output to the decoding buffer. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuitis simplified, and thereby the hardware scale is reduced, resulting in an inexpensive apparatus for reproducing a digital code sequence.

Coded signal reproduction apparatus

In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (to), and additional information () is generated for distinguishing GOP (Group of Pictures) user data () from the other main data. A VBV buffer simulation is performed using this additional information () to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.

Code conversion method and device thereof

A formatter is provided and, when a code sequence which matches a part ('00') of the head of a predetermined code sequence detected by a start code prefix detection unit, is detected, the start code prefix detection unit detects the residual part ('00', &#x2018;00&#x2019;, &#x2018;01&#x2019;, &#x2018;E0&#x2019;) of the detected predetermined code sequence to detect a pattern of (&#x2018;00&#x2019;, &#x2018;00&#x2019;, &#x2018;00&#x2019;), and the formatter outputs one (&#x2018;00&#x2019;). After the boundary of packets is defined, amongst data which are not transferred to a decoding buffer, data corresponding to code sequences other than the code sequence (&#x2018;00&#x2019;, &#x2018;00&#x2019;, &#x2018;01&#x2019;, &#x2018;E0&#x2019;) indicating that the packet boundary are output to the decoding buffer. Therefore, when separating a coded and multiplexed signal, control of an input buffer reading control circuit is simplified, and thereby the hardware scale is reduced, resulting in an inexpensive apparatus for reproducing a digital code sequence.

Apparatus for reproduction of encoded signal

When a digitized broadcast is recorded in a storage medium, a required capacity of the storage medium is firstly calculated on the basis of a bit-rate of digitized broadcast data and a recording time which is known in advance. If the remaining capacity of the storage medium is smaller than the required capacity of the storage medium, for example, a frame rate decimation and pixel reduction are performed upon a broadcast to be newly stored, a re-encoding processing is performed for the broadcast and then the resultant broadcast is stored in the storage medium. If the remaining storage capacity of the storage medium is larger than the required capacity of the storage medium and thus remains, a frame interpolation and pixel interpolation are performed for the broadcast to be stored and then a re-encoding processing is performed for the resultant broadcast in order to improve its image quality. As a result, recording of the broadcast data in the storage medium can be ensured.

Method and device for ensuring storage time for digital broadcast

A decoding devicedecodes a bit stream including a plurality of packets. Data corresponding to an access unit includes a first data portion-and a second data portion-. The decoding deviceincludes a packet regeneration sectionfor receiving a first packetand a second packetfollowing the first packet, and when the first packetincludes the first data portion-and the second packetincludes the second data portion-, producing a new packetincluding the data corresponding to the access unit by combining the first data portion-and the second data portion-. The decoding devicealso includes a decoding sectionfor decoding the data corresponding to the access unit. The new packetincludes information indicating a length of the data corresponding to the access unit.

Method and apparatus for decoding

A variable length encoding apparatus such as an encoding apparatus using the MPEG standard, wherein without degrading the precision of quantization step, the generated code bit amount is limited. Encoding is performed at the quantization step of required picture quality by an encoding part , and a bit stream is written in an external memory . The generated encoded bit amount is measured from the increment of a write pointer increased because of the writing in the external memory by a control unit . If the amount is larger than a preset value, the data is replaced with data leading to the same decoding result as those of the preceding or following reference picture by using a replacement pattern in accordance with the picture type and the position on a times series, and the data is written in the external memory , thus outputting the data as an output bit stream controlled to the generated code amount within an upper limit value.

Variable-length encoder

A picture data encoding apparatus includes a target bit amount determining part for calculating a target bit amount for each block according to a bit rate and a number of blocks to be converted; and a bit amount adjusting part for reducing a bit amount for each block to the target bit amount by means of reducing the bit amount for each code by converting run level information for each code into lower run level information.

Picture data encoding apparatus with bit amount adjustment

A frame memory is provided which has five fields each having N slots, and three additional slots. Each slot has a storage capacity to store eight image lines. Four fields of the five fields serve to store motion compensation reference frames. The remaining one field and the three additional slots are used for B-picture interlace conversion. Disposed in a control unit are a slot control memory, a write slot pointer, and a read slot pointer. For an image output unit to acquire information from the frame memory in a correct slot order, the contents of the slot control memory are updated at the time of performing write operation to enter information into the frame memory by a bit stream analysis unit.

Image processor

The present invention provides a video encoding apparatus including a video processor for performing video processing on input video data, a variable length encoder for performing variable length encoding on the processed (quantized) video data and for supplying the encoded data and a generated bit quantity, a DRAM for storing the encoded data that is output as a bitstream, a bitstream output circuit for computing, based on a value found by subtracting the generated bit quantity from a set bit quantity predetermined in advance, a period taken to read from the DRAM the bitstream and for outputting the bitstream as output video data in the computed period, and an arbiter for controlling the operations of the video processor, the variable length encoder, the DRAM, and the bitstream output circuit.

Video encoding apparatus and method

The present invention discloses an MPEG decoder for reproducing moving picture data. A first frame memory (FM0) and a second frame memory (FM1), each of which is composed of 2N slots, are provided. A third frame memory (FM2) is provided which is composed of N+4 slots. Each slot is provided with a memory capacity of eight lines. FM0 and FM1 each have a 1-frame memory capacity for storing reference frames for motion compensation. FM2, on the other hand, has a memory capacity of half a frame+32 lines for B-PICTURE interlace conversion. A slot control memory (SM) is further provided which is composed of 2N+6 words each of which stores a respective slot number of FM2. For an output section to read the slots of FM2 in the correct order, the contents of SM are updated by an control section at the time of the writing of FM2 by a decoding section.

Image information decoder with a reduced capacity frame memory

A variable-length-code decoder of this invention decodes an input bit stream including an input bit string having a codeword of a fixed-length code and a plurality of codewords of variable-length codes combined in a predetermined format. The decoder includes: a shifter for shifting the input bit string by a desired number of bits; a pattern detector for detecting a specific pattern in the bit string, and outputting a detection signal; two code tables provided for the respective variable-length codes, each code table having the length of each codeword (codeword length) and the decoded-word corresponding to the codeword, and outputting a codeword length and a decoded-word of a corresponding codeword based on the bit string output from the shifter; a processor for storing the format of the input bit string, outputting the length of the fixed-length code and decoded data of the fixed-length code, and selecting, for each of the variable-length codewords, one of the code tables to which the variable-length codeword belongs, based on the detection signal and the format; a codelength selector for selecting the codeword length or the fixed-length code, and for setting the shift amount for the input bit string in the shifter; and an output circuit for selectively outputting the decoded-word or the decoded data.

Apparatus and method for decoding variable-length code

A prefix data generating portion is arranged such that a bit string having bits in predetermined number supplied from a barrel shifter is compared, from the head part thereof, with predetermined patterns and that there is supplied a less-bit bank address assigned to the identical predetermined pattern. In a look-up table, a decoded data is addressed using (i) an upper address of the bank address and (ii) a lower address of a plurality of remaining bits of the code, other than the predetermined pattern. Accordingly, the look-up table can be addressed with an address in which the number of bits is smaller than that of the code. This reduces the look-up table in capacity, enabling to provide a variable-length decoding apparatus reduced in hardware size.

Variable-length decoding apparatus

A code sequence includes a header code consisting of a series n 0 bits terminated by a 1 bit. A shifter outputs the code sequence in bit strings. Each bit string is made up of plural bits. A priority encoder performs arithmetic operation to count the number of consecutive 0 bits from the most significant bit of each bit string. An accumulator adds the results found by the priority encoder. A comparator compares the sum found by the accumulator with a set value n. The comparator outputs a coincidence signal if these two values are found equal. The priority encoder outputs a 1-bit-inclusion indication signal if a bit string includes a 1 bit. Upon receipt of the coincidence signal and the 1-bit-inclusion indication signal, a first AND circuit outputs a header detection signal. As a result of such arrangement, the code sequence is processed in units of plural bits, whereupon high-speed header code detection is accomplished without requiring the shifter and the accumulator, both of which are components of a header detector, to operate at high speed.

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Osaka, Japan

Eiji Miyagoshi