Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Eiji Masuda

Kenji Matsuo

Yasuhiko Fujita

Yasoji Suzuki

Hiroaki Suzuki

Tetsuo Yamaguchi

Teruaki Tanaka

Shigemi Sakamoto

Hiroyuki Watanabe

Chikara Sato

Akira Nishimura

Akira Yamaguchi

Hiroshi Kawasaki

Terufumi Takasaki

A plurality of semiconductor elements or element groups in which the shapes, for example, the channel lengths, are slightly different from each other, are designed in advance, and are then fabricated on a semiconductor substrate. Once the main part of the elements, for example, the channel lengths, have been formed on the substrate, the shapes of these elements are measured. According to the measured data, particular elements or element groups which satisfy the required design values of the elements are selected for wirings and connectings to make products. So, the fabrication yield of the finished procucts, for example, made by the master slice approach or the gate array approach can be greatly improved.

Apparatus and method for the fabrication of semiconductor circuits

Disclosed is a clock supply circuit operating in a first phase and a second phase. Each buffer provided in each channel operating in the second phase has the same drive ability, and the number of flip-flops which are dependent on each buffer is the same. When the number of the flip-flops is not the same, capacitance means is provided in each channel in order to make conditions uniform for operation in the second phase.

Clock supply circuit having adjustment capacitance

Two basic logical circuits having a transfer gate section consisting of a channel MOS transistor and a P-channel MOS transistor, the gate electrode of the former being connected to a first input terminal to which a first input signal is applied, the gate electrode of the latter being connected to a second input terminal, the source electrodes of the N-channel and P-channel MOS transistors connected in parallel being connected to a third input terminal to which a third input signal is applied, and either a P-channel MOS switching transistor or a N-channel MOS transistsor. When the P-channel MOS transistor is used as the switching transistor, its gate electrode is connected to the first input terminal and the remaining electrodes are connected to an output terminal and the second input terminal, thereby realizing either NAND operation or OR operation by the same circuit construction but in accordance with the combination of the three input signals. On the other hand, when the N-channel MOS transistor is used as the switching transistor, its gate electrode is connected to the second input terminal and the remaining electrodes thereof are connected to the output terminal and the first input terminal, thereby realizing either AND or NOR operation by the same circuit construction but in accordance with the different combination of the three input signals applied to the three imput terminals.

Logical circuits for performing logical functions without a power supply

The memory device memorizes a number corresponding to a plurality of digits, for example, a unit phone number using a first memory array. A desired number is obtained by selecting a Y address. A readout operation is executed by inputting whole data selected by a Y address to a second memory array at once and outputting data sequentially from the second memory array by one digit. A write operation is executed by inputting data sequentially to the second memory array by one digit and outputting data from the second memory array to the first memory array at once.

Memory device

An input signal level detecting circuit includes a first inverter group circuit having first and second inverters connected in series, and a second inverter group circuit having third and fourth inverters connected in series. The input terminals of the first and third inverters are supplied with a signal having first and second levels to be detected. The output terminals of the second and fourth inverters are connected to set and reset terminals of the flip-flop circuit. When the mean level of the first and second levels is V.sub.TM and the threshold voltages of the first to fourth inverters are V.sub.T1 to V.sub.T4, respectively, the relations V.sub.T1 &gt;V.sub.TM ; V.sub.T2 &lt;V.sub.TM ; V.sub.T3 &lt;V.sub.TM and V.sub.T4 &gt;T.sub.TM are satisfied.

Input signal level detecting circuit

In a D/A converter, a reference voltage is divided into a plurality of divided voltages by a plurality of resistors connected in series. The divided voltages are respectively selected by switches which are turned on according to the contents of a digital input. With the use of an expanding bit or bits, a plurality of the switches are simultaneously turned on.

Digital-to-analog converter

A voltage comparison circuit having an amplification circuit which includes an inverting amplifier and a switching MOS transistor for setting an operation point of the inverting amplifier connected between input and output terminals of the inverting amplifier. The amplification circuit further includes at least one low-pass filter connected in a closed loop including the inverting amplifier and the switching MOS transistor.

Voltage comparison circuit with ripple component elimination

A dual-tone multiple-frequency (DTMF)-signal generating apparatus of the present invention is provided with a high-group frequency divider and a low-group frequency divider for dividing a reference frequency signal into high-group frequencies and low-group frequencies, respectively. The respective outputs from the high-group divider and the low-group divider are supplied to a high-group-sine-wave-signal generator and a low-group-sine-wave-signal generator. The high- and low-group-sine-wave-signal generators comprise a plurality of bi-stable circuits and include shift registers for sequentially shifting a divided input signal within a predetermined period, a plurality of switches which selectively pass high or low level signal corresponding to the outputs of the respective bi-stable circuits, and a plurality of capacitive elements in which the terminals on one side thereof are supplied with the high or low level passed by the plurality of switches, and the terminals on the other side thereof are commonly connected, the high or low level being applied to the comon connection for every cycle of the shift registers to produce the high- and low-group-sine-wave signals from the common connection. The respective sine wave signals are level converting by a high-group level converter comprising a capacitor and a switch and by a low-group level converter comprising a capacitor and a switch. The level converted high- and low-group-sine-wave signals are combined by a mixer comprising buffer amplifiers, resistors and a transistor, thereby obtaining a DTMF signal.

Dual-tone multiple-frequency-signal generating apparatus

A digital-analog converter wherein reference voltage is divided by a first string-like resistor array, whose two adjacent outputs are selected by a first switch array depending upon the contents of upper bits of a digital signal and applied to the both ends of a second string-like resistor array, and one of switches in a second switch array is selectively turned on responsive to the contents of lower bits of said digital signal to pick up one of the divided voltages of said second resistor array.

Digital-analog converter

A semiconductor switching circuit includes a MOS inverter and a switching MOS transistor for executing a switching operation in response to the output signal from the MOS inverter. The semiconductor switching circuit further includes a low-pass filter coupled between the MOS inverter and the gate of the switching MOS transistor.

Semiconductor sample and hold switching circuit

A parallel analog-to-digital converter circuit comprises a plurality of level comparator circuits and a plurality of detectors. The level comparator circuits compare the level of one analog input signal with a plurality of reference levels. Any two or more level comparator circuits which receive consecutive reference levels from one set. Each of the detectors determines whether or not the output signals from the level comparator circuits of one set are in a specified state. According to the number of sets of level comparator circuits whose output signals are detected to be in the specified state, it is determined whether or not the analog-to-digital converter circuit functions correctly. the upper limit of the speed of analog-to-digital conversion can be determined according to this number of sets.

Parallel analog-to-digital converter circuit

Disclosed is a differential amplifier circuit in which attenuators are provided to the inverting input terminal and non-inverting input terminal of the differential amplifier, respectively, whereby the amplitudes of input voltages are attenuated so that the amplitudes may fall within a linear range of operation of the differential amplifier, and whereby the input voltages are set at an operating point of the differential amplifier.

Differential amplifier circuit

An input voltage sampler samples the difference between two input voltages. An alternate switch switches at a period which is longer than twice the sampling period. The voltage difference is supplied through the alternate switch to a plurality of amplifiers. Prior to starting the amplifying operation, operating point setting circuits set the input level to the amplifiers at the operating point.

Autozeroed comparator

A differential voltage amplifier comprises a first and second capacitive coupling type amplifiers in each of which an autozeroed mode period for setting an operating point and a signal amplifying mode period for amplifying an input voltage are alternately set up, and the autozeroed mode periods in said first and second amplifier are shifted from each other, first and second mode selector for alternately setting up the autozeroed mode and the signal amplifying mode in the first and second capacitive coupling type amplifiers, first and second signal selectors provided corresponding to the first and second capacitive coupling type amplifiers, the first and second signal selectors alternately selecting a reference voltage and an input signal voltage to apply the selected signal to the first and second capacitive coupling type amplifiers, the first and second signal selectors further selecting the reference voltage corresponding to the autozeroed mode periods of the first and second capacitive coupling type amplifiers and the input signal voltage corresponding to the signal amplifying mode periods, and a selector for selecting the amplified signal output from the first and second capacitive coupling type amplifiers when the first and second capacitive coupling type amplifiers are in the signal amplifying mode.

Differential voltage amplifier

An operational amplifier which comprises a first amplifying circuit; a second amplifying circuit which is connected to the first amplifying circuit and carries out inverting amplification; a third amplifying circuit which is connected to the second amplifying circuit, carries out noninverting amplification and has a gain of substantially 1; a first feedback circuit which is connected between the output and input terminals of the second amplifying circuit and carries out phase-compensation; and a second feedback circuit which is connected between the output terminal of the third amplifying circuit and the input terminal of the second amplifying circuit, and carries out phase-compensation.

Growing community of inventors

Kawasaki, Japan

Eiji Masuda