Kabushiki Kaisha Toshiba

Eiji Kamiya

Kazuhiro Shimizu

Hiroaki Hazama

Kazuhito Narita

Hirohisa Iizuka

Norio Ohtani

Riichiro Shirota

Seiichi Aritome

Yuji Takeuchi

Toshitake Yaegashi

Norihisa Arai

A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.

Non-volatile semiconductor memory device and method of manufacturing the same

A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, and including a first gate insulator having a first thickness. The device further includes a high-voltage transistor circuit formed on the semiconductor substrate, and including a second gate insulator having a second thickness greater than the first thickness, and a peripheral circuit formed on the semiconductor substrate, and including the second gate insulator.

A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes forming a resist pattern so that an opening between select gates of a select gate transistor is formed in a memory cell region, implanting threshold-adjusting ions under the select gate with the resist pattern serving as a mask and removing an oxide film, forming a nitride film and an interlayer insulation film after the resist pattern has been removed, forming a resist pattern used to form a contact hole between the select gates and a contact hole for a transistor to be formed in the peripheral circuit region, the transistor having a higher breakdown voltage than a memory cell transistor and etching the interlayer insulation film, the nitride film and the gate insulation film individually with the resist pattern serving as a mask.

In a memory cell, a gate oxide film is formed on a surface of semiconductor substrate and a first floating gate is formed on the gate oxide film. An insulating film is formed on a first floating gate and a second floating gate is formed on the insulating film. The first and second floating gates constitute a floating gate in the memory cell. An insulating film between the first floating gate and the second floating gate acts as an etching stopper when a polysilicon constituting the second floating gate is etched.

Nonvolatile semiconductor memory device having a two-layer gate structure and method for manufacturing the same

A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.

Semiconductor device, semiconductor element and method for producing same

The present invention is directed to a flash EEPROM in which a plurality of resist patterns are arranged like an island such that only an interlayer insulation film formed on a field oxide film is left in order to insulate drain diffusion layers of cell transistors in the row direction from each other when contacts of a memory cell group are subjected to PEP. Using the island-like resist patterns as masks, contact holes communicating with both the drain diffusion layers and source diffusion layers are made. Since, therefore, drain and source contact holes are arranged in matrix, the PEP margin can greatly be increased, thereby making it possible to prevent the problems of forming no contact holes and causing a short circuit between the gate and contact from arising.

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Yokkaichi, Japan

Eiji Kamiya