Kabushiki Kaisha Toshiba

Fujitsu Hitachi Plasma Display Limited

Eiji Ito

Koji Hashimoto

Hideyuki Kinoshita

Tetsuya Kamigaki

Tomokatsu Kishi

Hirofumi Inoue

Noriaki Setoguchi

Takahiro Takamori

Hideyuki Tabata

Hiroyuki Nagashima

Yoshikazu Kanazawa

Kazuyoshi Yamada

Makoto Onozawa

Hideaki Ohki

Hitoshi Ito

Masaki Kamada

Masanori Komura

Mitsuhiro Noguchi

Masahiro Kiyotoshi

Tadashi Iguchi

Hitoshi Hirakawa

Shinsuke Tanaka

Naoya Hayamizu

Hiroyuki Fukumizu

Katsuhiro Sato

Kenji Aoyama

Moto Yabuki

Takashi Shiizaki

Ken Kumakura

Shingo Nakajima

Satoru Nishimura

Kazuhito Nishitani

Machiko Tsukiji

A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n&#x2212;3)-th (n is a positive integer) and (4n&#x2212;2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n&#x2212;1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

Nonvolatile semiconductor memory device and producing method thereof

A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Semiconductor device having dummy bit lines wider than bit lines

A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.

Nonvolatile semiconductor memory device including a via-hole with a narrowing cross-section and method of manufacturing the same

NAND flash memory having bit line with smaller width than width of peripheral interconnect line

A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Nonvolatile semiconductor memory device using a variable resistance film and method of manufacturing the same

A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

Nonvolatile semiconductor memory device including via-holes continuously formed through plural cell array layers

A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.

Semiconductor memory device

Manufacturing a nonvolatile storage device including: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a substrate; processing the first electrode film and the first storage unit film into a strip shape; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the sacrifice layer; forming a mask layer on the second electrode film; processing the second electrode film into a strip shape using the mask layer; removing a portion of the first storage unit film exposed from the sacrifice layer using the mask layer processing the first storage unit film into a columnar shape, removing the sacrifice layer exposing the first storage unit film; and removing the exposed first storage unit film.

Method for manufacturing nonvolatile storage device

A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

Semiconductor memory device and method for manufacturing the same

Method of manufacturing semiconductor device

A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.

Semiconductor device with wirings having varying lengths

A method of manufacturing a semiconductor device, comprises forming a first mask pattern on an under-layer region, forming a plurality of dummy-line patterns on the under-layer region, the dummy-line patterns being arranged at a first pitch, forming second mask patterns having mask parts provided on long sides of the dummy-line patterns, removing the dummy-line patterns, and etching the under-layer region by using the first mask pattern and the mask parts as a mask.

Method of manufacturing a semiconductor device

A low-cost capacitive load drive circuit, in which a reference voltage, a first voltage, and a second voltage are supplied to a capacitive load, and a plasma display apparatus using it, have been disclosed. The capacitive load drive circuit comprises a reference voltage switch the breakdown voltage of which is properly adjusted, a first switch, a reference voltage phase adjusting circuit, and a first phase adjusting circuit, and malfunctions due to the difference in switching characteristics can be prevented from occurring even when devices of different breakdown voltages are used.

Capacitive load drive circuit and plasma display apparatus

The plasma display apparatus, in which the light emission efficiency is improved, has been disclosed. The fourth electrodes, which extend in the same direction of the first electrodes (X electrode) and the second electrodes (Y electrodes) and are exposed into the discharge space, are provided between the first and the second electrodes where the sustaining discharge is carried out, and when the sustain action is carried out, the fixed voltage between the voltage applied to the first electrode and that applied to the second electrode is applied to the fourth electrode provided between the first and the second electrodes where the sustain action is carried out in order to make the electric field between the first and the second electrodes uniform.

Plasma display apparatus

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Kawasaki, Japan

Eiji Ito