Fujitsu Corporation

Eiji Itaya

Yoshiaki Kumagai

Yoichi Endo

Hiroshi Kurihara

Takaharu Nakamura

Takeshi Takano

Tadayoshi Katoh

Fumihiko Kobayashi

Sadao Takenaka

A radio transmission system is provided which includes a master station and a plurality of series connected substations connected to the master station via a radio channel. First receiving unit receives a plurality of modulated waves which have been modulated by means of spread spectrum. Accordingly, demodulating unit may only have a capability to process a baseband signal destined therefor, in order to demodulate the modulated wave destined therefor from among the modulated waves. On the other hand, the modulated waves received by the first receiving unit are transmitted by first transmitting unit in a first transmission direction to an adjacent substation, and thus are relayed as they are without being demodulated or modulated in the middle.

Radio transmission system

An automatic frequency control (AFC) circuit receives input signals and generates converted signals by mixing the input signals with a local oscillation signal. An extraction circuit extracts a pilot signal, if present, from the input signals and provides the pilot signal to a switch. A frequency divider divides a frequency of the local oscillation signal output from a voltage control oscillator, and provides the frequency-divided local oscillation signal to the switch. The output of the switch is compared with a reference frequency in a phase comparator which generates a comparison result which controls the voltage controlled oscillator. If the pilot signal is not present, the switch selects the frequency-divided oscillation signal, to construct a phase-locked loop to stabilize the frequency of the local oscillation signal. Alternatively, an AFC circuit includes a frequency divider for selectively dividing a frequency of a pilot signal included in the converted signal. Various frequencies of the pilot signal can be received by altering a division number in the frequency divider.

Automatic frequency control circuit selectively using frequency-divided

A loop testable radio transmitter/receiver includes a transmission system which includes a transmission frequency converting unit and a transmission signal filter unit. A receiving system is provided, including a receiving signal filter and a receiving frequency converter. The transmitter/receiver further includes a transmitter/receive sharing unit, a transmission signal looping unit for attenuating the transmission signal of the transmission system and for looping back it to the receiving system, and a shifter arranged to the output side of the receiving frequency converting unit in the receiving system for converting an intermediate frequency of a signal converted by the receiving frequency converting unit into the receiving input frequency of a modulator/demodulator.

Loop testable radio transmitters/receivers

An automatic transmission level control device used in a multi-carrier communication system includes a gain controller for controlling a level of a transmission signal, a transmitter for amplifying the transmission signal, and a hybrid circuit for extracting a part of power of the transmission signal from the transmitter. A level control circuit adjusts a gain of the gain controller on the basis of a magnitude of the transmission signal and data indicating a number of carriers included in the transmission signal. A carrier detection unit filters the transmission signal and generates the data indicating the number of carriers included therein.

Automatic transmission level control device

A signal generator having a switching function includes a first oscillation circuit, a second oscillation circuit, a frequency-division circuit and a combination circuit. The first oscillation circuit outputs a first frequency signal having a first frequency and a reset signal synchronized with the first frequency signal. The second oscillation circuit outputs a second frequency signal having a second frequency which is N times higher than the first frequency. The frequency-division circuit frequency-divides the second frequency signal by N, resets a value for frequency-division based on the reset signal and generates a divided second frequency signal. The combination circuit combines the first frequency signal and the divided second frequency signal and outputs a combined signal.

Signal generator having backup oscillator switching circuit

A phase locked loop for extracting an output signal synchronized with an input signal. The present invention is structured so that a phase locked loop can prevent loss of control due to high frequency noise generated by a level conversion circuit in the feedback loop after oscillation of the VCO has stopped due to a failure. The phase locked loop includes an exchange circuit connected between an output of the phase detector and an input to the feedback loop. When the exchange circuit determines that the output of the phase detector is below a reference voltage, it applies a signal having a frequency which is lower than that of the input signal to the phase detector in place of a signal from a frequency divider in the feedback loop. In such a case, the phase detector outputs a pulse signal which restarts oscillation of the VCO and leads to normal phase control operation.

Phase locked loop having circuit for recovering from oscillation stoppage

A frequency synthesizer having an intermittently operated PLL circuit in which power is intermittently applied to a prescaler to reduce power consumption. The PLL circuit is operated such that fluctuations in the frequency synthesizer output frequency do not occur. This stability in the output frequency results from selectively providing signals to the phase comparator within the PLL circuit only during a time period beginning after power is applied to the prescaler and ending before power is removed from the prescaler.

Intermittently operated frequency synthesizer having suppressed

A phase synchronizing circuit, wherein two phase detectors are used in quadrature to detect the phase of an input signal and to avoid hang-up when the phase of the input signal changes abruptly by 180.degree.. The two detected phase signals are then multiplied by a locally generated reference signal and re-combined, so that a synchronized output signal having reduced phase jitter results. This circuit is also incorporated in an N-phase PSK system, where it is used as a synchronizer and not as a demodulator. In a receiver for such a PSK system, the frequency of the received signal is multiplied by N, the phase synchronizer circuit of the invention is then used to extract the carrier (at a N times higher frequency), and a divider is then used to convert the synchronized carrier provided by the synchronizer circuit of the invention down to the original frequency.

Phase synchronizing circuit

A carrier regeneration circuit regenerates the carrier from the QAM (Quadrature Amplitude Modulated) received signal, as produced and transmitted by a quadrature partial response modulation system wherein quadrature-related carriers (i.e., having a phase difference of 90.degree.) of the same frequency are amplitude modulated with two parallel signals which have been subject to partial response conversion. The carrier regeneration circuit comprises a probability decision circuit which decides the probability of generation of particular demodulated data code combinations, and a carrier regeneration control circuit which maintains the phase ambiguity of the regenerated carrier within an integer multiple of 90.degree.. The control circuit responds to the output of the probability decision circuit for selectively shifting the phase of the regenerated carrier by 45.degree..

Growing community of inventors

Kawasaki, Japan

Eiji Itaya