Fujitsu Corporation

Fujitsu Vlsi Limited

Eiji Fujine

Kazushige Itazu

Rieko Suzuki

Yukimi Nishiwaki

Kiyoshi Saida

Yoshihiro Kamiya

Yoshitaka Uchida

Takako Murakami

Teruhisa Tsuyuki

Kazunori Kawazoe

Takeshi Shimazaki

Masahiro Suzuki

Takashi Kurihara

Takanori Nawa

Masahito Isoda

Hiroshi Yuyama

Kenji Wada

The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven distribution of a floor plan taken into account. In Step S, design information (Core size CS, core ring width CW, block shape BS, macro shape MS, block current BI, macro current MI, etc.) is inputted into a simulator. In Step S, information regarding a floor plan (Block position BP, macro position MP, power I/O position IOP) is inputted into the simulator by a designer. In Step S, the power unit management table is initialized, and resistance modeling and current source modeling are also carried out. In Step S(FIG.), the static IR drop is calculated based on the power unit management table CT obtained in Step S

Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program

Disclosed are a suitable power supply network analyzing method which executes power supply network analysis of a large-scale circuit in a short period of time with fewer computer hardware resources, a computer program which executes the power supply network analyzing method, a storage medium and a power supply network analyzing apparatus. An entire net list is extracted by converting circuit elements to current sources and dividing power supply lines into resistor elements, based on design information and physical information. Next, a portion of the power supply network which includes the current sources and in which the resistor elements are connected in series is selected. A partial net list is extracted to execute circuit compression by allocating the current sources to circuit elements in the selected portion. Then, the compressed net list is set in the entire net list to simplify the entire net list and power supply network analysis is performed. In case where analysis of the partial net list has not been completed, the results of the analysis of the entire net list is set to both end nodes and analysis is executed again. This can ensure hierarchical analysis.

Power supply network analyzing method, computer program for executing the method, storage medium and power supply network analyzing apparatus

A method and apparatus for generating external power wiring layout data for a semiconductor integrated circuit device determines an optimum layout without performing time consuming circuit simulation. An external power wiring supplies power to each of the functional blocks of the device. Design information is used to calculate a current consumption ratio for each power supply terminal of each functional block. Then, the current consumption for each power supply terminal is calculated using the calculated current consumption ratios. An external power wiring network is generated based on the calculated current consumption for each terminal. The generated external power wiring network is then analyzed and voltage and current values for each part of the network are calculated. Using the calculated voltage and current values, the wires are then optimally sized.

Method and apparatus for generating layout data for a semiconductor integrated circuit device

According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.

Manufacturing method and apparatus of a semiconductor integrated circuit

Growing community of inventors

Kasugai, Japan

Eiji Fujine