Elpida Memory, Inc.

Nec Corporation

Eiichiro Kakehashi

Kazuhiko Kajigaya

Yoshitaka Nakamura

Noriaki Ikeda

Yuki Togashi

Hiroyuki Kitamura

Hiroyasu Kitajima

A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each having a structure in which dielectric material is sandwiched between two electrodes, and the memory cell array is divided into a plurality of areas capable of being designated. The forming controller controls to perform 'forming' for the first memory cells in an area selectively designated from the plurality of areas of the memory cell array, and as a result of the forming, the first memory cells are changed to non-volatile second memory cells.

Semiconductor memory device and information processing system

A semiconductor device includes cylindrical capacitors each including corresponding cylindrical electrodes. Each cylindrical electrode includes hemispherical silicon grains. The hemispherical silicon grains protruding from an upper region of the cylindrical electrode have a large size, and the hemispherical silicon grains protruding from a lower region of the cylindrical electrode have a small size or the lower region of the cylindrical electrode has no hemispherical silicon grains.

Hemispherical silicon grain capacitor with variable grain size

A formation method of an alignment mark is provided. After an etching resist part is formed on a first dielectric layer, a second dielectric layer is formed on the first dielectric layer to cover the etching resist part. Then, the second dielectric layer is selectively etched to form a recess uncovering the etching resists part using a first patterned lithography resist film as a mask. In this etching process, the first dielectric layer is prevented from being etched in the recess of the second dielectric layer by the etching resist part. A layer to be patterned is formed on the second dielectric layer and a second patterned lithography resist film is formed on the layer to be patterned. The second patterned lithography resist film has such a shape that a part of the second lithography resist film is left in the recess of the second dielectric layer. The part of the second lithography resist film in the recess has a height difference approximately equal to or less than the thickness of the second dielectric layer from another part of the second lithography resist film outside the recess. The alignment error of a pattern of the second lithography resist film with respect to a pattern of the second dielectric layer is measured correctly.

Method of forming alignment mark and fabricating semiconductor device

Growing community of inventors

Tokyo, Japan

Eiichiro Kakehashi