National Institute of Advanced Industrial Science and Technology

Sharp Kabushiki Kaisha Corporation

Other

Agency of Industrial Science and Technology

Evolvable System Research Institute, Inc.

Eiichi Takahashi

Tetsuya Higuchi

Masahiro Murakawa

Yuji Kasai

Munehiro Uratani

Kenji Toda

Yutaka Takafuji

Masahiro Adachi

Shinji Shimada

Nobuyoshi Nagashima

Tadanori Hishida

Shuhei Yasuda

Kanji Otsuka

Tamotsu Usami

Hidenori Sakanashi

Yasunori Nishimura

Hirokazu Nosato

Takao Nomura

Kiyoshi Toda

Takehiko Segawa

Yosuke Iijima

Masahiro Yasuda

Yuudai Yamazaki

Masaya Iwata

An apparatus for cleaning a surface of an optical window includes a first electrode that is provided inside the optical window and is covered with a dielectric material forming the optical window. A second electrode is provided around the optical window and is exposed on at least one surface of the optical window. A power supply is electrically coupled between the first electrode and the second electrode. The apparatus further includes a controller that controls the power supply so as to generate dielectric barrier discharge along the surface of the optical window by applying a high-frequency or pulsed voltage between the first electrode and the second electrode.

Cleaning apparatus for optical window, engine, and method for cleaning optical window of engine

The ultrasound examination system automatically detects a lesion, based on a dynamic image including a plurality of frame arrays that are temporally continuous and are output from the ultrasound examination apparatus with an ultrasonic probe being manipulated. Detection accuracy of the ultrasound examination system can be increased. A feature extractor in a frame checker extracts cubic higher-order local autocorrelation features from each frame of a plurality frames that constitute a dynamic image of a human body part as obtained from an ultrasound examination apparatus while an examiner manipulates an ultrasonic probe on the examinee. A final determinator determines that the frame in question is a normal frame when a speed determinator determines that the speed of the ultrasonic probe is not a normal speed even though the frame in question can be determined as an abnormal frame containing a lesion.

System and method for ultrasound examination

A master node () sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node () is set in the identification signal time slot, the master node () and slave nodes (to) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.

Serial bus transmission system

A network system by the present invention can quickly detect viruses and does not easily become a new cause of vulnerability. A packet data comparator branches inputted packet data into three branches, and includes an additional pattern matching unit which compares the branched data with the stored data and performs matching with collation patterns stored in a rewritable storage area, a fixed pattern matching unit which compares the branched data with the stored data and performs the matching with a logical operation configured with known collation patterns, a notification packet matching unit which compares the branched data with the stored data and finds a notification packet, and an identity detection aggregation unit which aggregates results from the respective matching units. Moreover, a virus filter, a virus checker, and a secure network system are realized by using the present invention.

Packet data comparator as well as virus filter, virus checker and network system using the same

A power consumption controlling apparatus controls power consumption of a high frequency amplifier to reduce the power consumption by adjusting a power supply voltage and a bias voltage of the high frequency amplifier which amplifies a high frequency transmitting signal. The power consumption controlling apparatus includes: a receiving circuit for receiving the high frequency transmitting signal amplified by the high frequency amplifier; an evaluating section for evaluating whether or not a receiving signal obtained from the receiving circuit satisfies a predetermined quality; and an adjusting section for adjusting the power supply voltage and the bias voltage in a range in which the receiving signal evaluated by the evaluating section satisfies the predetermined quality.

Power consumption controlling apparatus for high frequency amplifier

Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program

A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.

High-speed signal transmission system

A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.

Digital circuit having delay circuit for adjustment of clock signal timing

A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.

Bus driver with well voltage control section

A digital system that performs a specified function by performing digital processing according to one or more clock signals is provided with a plurality of delay elements which are respectively inserted in a plurality of clock circuits that supply the clock signals in the digital system and each of which is composed of a circuit element that changes a delay time according to a value indicated by a control signal, and a plurality of holding circuits that hold a plurality of control signals to be given to the plurality of delay elements. In the plurality of holding circuits, a value of the control signals held by these holding circuits is changed by external devices according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing.

Timing adjustment of clock signals in a digital circuit

A liquid crystal display device includes: an array substrate; a counter substrate facing the array substrate; and a liquid crystal layer interposed between the array substrate and the counter substrate, wherein the array substrate includes: a plurality of pixel electrodes arranged in a matrix in a display region; a plurality of gate lines; a plurality of source lines which cross the plurality of gate lines; an insulating layer provided between the plurality of gate lines and the plurality of source lines; a plurality of switching elements respectively connected to respective ones of the plurality of the gate lines, the plurality of source lines, and the plurality of pixel electrodes; and a short ring, a plurality of first inspection signal voltage input terminals and a plurality of depletion-type thin film transistors (DTFT) provided in a peripheral region adjacent the display region, and wherein each of the plurality of gate lines and the plurality of source lines is connected to the short ring via respective ones of the plurality of first inspection signal voltage input terminals and respective ones of the plurality of depletion-type thin film transistors, and the plurality of depletion-type thin film transistors is located between the short ring and the plurality of first inspection signal voltage input terminals, the plurality of depletion-type thin film transistors control electrical conduction between the short ring and the plurality of gate lines and source lines.

Liquid crystal display device having DTFTs connected to a short ring

A transmission type or projection type liquid crystal display device includes a light source and an active matrix type liquid crystal display panel provided with a thin film transistor arrangement. A shielding film is included for cutting off light incident upon the thin film transistor arrangement from the light source. Electrode terminals of the liquid crystal display panel and outputs of driving LSI circuits are connected to each other by flexible substrates with the connected portions between the electrode terminals of the liquid crystal display panel and the flexible substrates protected by a connected portion protecting resin. The liquid crystal display device is further provided with a light shielding device for covering at least the protecting resin portion of the liquid crystal display panel, so as to prevent light of the light source from entering the region of the connecting portion protecting resin.

Liquid crystal display device with light shield

A method of forming an orientation film of a liquid-crystal display device having two electrode plates and a liquid-crystal cell between the two electrode plates includes the steps of forming an organic film on a partial or overall surface of at least one plate of the two electrode plates and radiating accelerated ions containing neutral atoms to the partial or overall surface of the organic film coated on the plate. The organic film consists of liquid-crystal molecules. The radiation is done for etching the organic film and orienting the liquid-crystal molecules in a unidirectional manner. The angle of incidence of the accelerated ions is defined as 40.degree. to 80.degree. with respect to a normal line of the plate. It results in offering even orientation of liquid-crystal molecules included in the liquid-crystal display device.

Growing community of inventors

Tsukuba, Japan

Eiichi Takahashi