Nec Electronics Corporation

Renesas Electronics Corporation

International Business Machines Corporation

Eiichi Soda

Sivananda K Kanakasabapathy

Yunpeng Yin

Sachiko Yabe

Hitoshi Ishimori

An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.

Method of making a semiconductor device

The present invention provides a method for processing an etching-target film, which can achieve both of a highly precise dry etching process and a reduction of LER. A method for processing an etching-target film, comprises: forming, in sequence from the bottom, an organic mask layer, a silicon-containing layerand a resist layer, over an etching-target film; forming a predetermined pattern in the resist layerby a photolithography process; etching the silicon-containing layerthrough a mask of the resist layerby employing a first etching gas; etching the organic mask layerthrough a mask of the etched silicon-containing layerby employing a second etching gas; and etching the etching-target film through a mask of the etched organic mask layerby employing a third etching gas, wherein the first etching gas contains trifluoroiodomethane (CFI).

Method for manufacturing semiconductor device, and method for processing etching-target film

Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second insulating film with a porous structure on the first insulating film; (d) forming a third insulating film different from the second insulating film on the second insulating film; (e) forming a via hole in the second and third insulating film by dry etching of the third insulating films; (f) removing a part of the first insulating film such that the surface of the first conductive layer is exposed at the bottom of the via hole and (g) forming a second conductive material film layer so as to fill the via hole.

Method for manufacturing a semiconductor device

A method of patterning a multiple-layered resist film and a method of manufacturing a semiconductor device, which can provide an improved reliability of the semiconductor devices and a reduced operation time for an etch process, are provided. A method of patterning a multiple-layered resist film according to the present invention include: forming a lower layer resist filmon a semiconductor substrate; forming a silicon-containing upper layer resist film on the lower layer resist film; patterning the silicon-containing upper layer resist film into a predetermined geometry; and performing dry etching process for removing the lower layer resist filmthrough a mask of the patterned silicon-containing upper layer resist filmemploying an etching gas containing oxygen (O) gas and argon (Ar) gas at a pressure within a range of from 0.075 mTorr to 50 mTorr both inclusive.

Method of patterning multiple-layered resist film and method of manufacturing semiconductor device

A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The method includes: forming a via hole in the interlayer insulating film; forming a resin film plugging the via hole on the interlayer insulating film; etching the resin film exposed outside the via hole off with an etching gas mainly containing an active hydrogen species to form a dummy plug composed of the resin film in the via hole; forming a resist mask having an opening for an interconnect on the dummy plug and on the interlayer insulating film.

Method for manufacturing electronic device

A method of fabricating a semiconductor device of the present invention includes a step (S) of judging whether an interconnect pitch of an interconnect pattern having the smallest interconnect pitch out of all interconnect patterns to be formed in the insulating film is not larger than a predetermined value or not; a step (S) of determining the thickness of the lower resist film corresponding to the interconnect pitch, if the interconnect pitch is judged as being not larger than a predetermined pitch, in the step of judging whether the interconnect pitch is not smaller than the predetermined value; and a step (S) of forming, on the insulating film, the lower resist film having the thickness determined in step Sby using a multi-layered resist.

Method of fabricating semiconductor device

A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The method includes: forming a via hole in the interlayer insulating film; forming a resin film, plugging the via hole, on the interlayer insulating film; forming a resist mask having an opening for an interconnect on the interlayer insulating film; and etching the interlayer insulating film through an etching mask of the resist mask to form a trench for the interconnect connected with the via hole. The resin film is being capable of trapping a basic substance.

A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. The dry etching of the third insulating film and the second insulating film is performed using a gas containing fluorine at a pressure of 0.1 Pa to 4 Pa. Ashing is preferably performed using at least one of hydrogen and an inert gas.

Growing community of inventors

Ibaraki, Japan

Eiichi Soda