Kabushiki Kaisha Toshiba

Eiichi Makino

Masaru Koyanagi

Shigeo Ohshima

Masahiro Yoshihara

Yohji Watanabe

Naohisa Okumura

Daisuke Kato

Kazuyoshi Muraoka

Mami Kawabata

A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a first component, a second component, a plurality of first, second and third contacts, and a plurality of signal lines having a plurality of first wires, and connecting the first and second component, each of the first wires having a first, second, third and fourth part, each of the parts having a resistivity, the second part having a first resistivity, a different value of the first resistance being set for each of the plurality of first wires, the first, third and fourth parts having a second or third resistivity which is lower than the first resistivity, the first and second part being electrically connected in series by the first contact, the second and third part being electrically connected in series by the second contact, and the third and fourth part being electrically connected in series by the third contact.

Semiconductor integrated circuit device and method of arranging wirings in the semiconductor integrated circuit device

A semiconductor device including a circuit substrate including n number of terminals; a semiconductor chip provided on the circuit substrate and including n number of terminals; and a relay chip including a triangular substrate having a first side, a second side and a third side which form triangle, n number of first terminals located along the first side, n number of second terminals located along the second side, and a plurality of wires connecting the first terminals and the second terminals respectively; a first wire connecting each of the n number of terminals of the circuit substrate to a corresponding first terminal among the n number of first terminals; and a second wire connecting each of the n number of terminals of the semiconductor chip to a corresponding second terminal among the n number of second terminals.

Semiconductor device, relay chip, and method for producing relay chip

This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.

A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data program control section which programs a plurality of first multi-bits data each having a first number of bits, or a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, to said plurality of memory cell arrays, a page buffer circuit which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said word lines from said plurality of memory cell arrays, a data transfer section which transfers said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said second number of bits from said page buffer circuit synchronized with a second clock signal having a cycle which is twice that of a first clock signal, and a data output section which receives said data from said data transfer section and outputs externally said data in synchronization with said first clock signal.

Nonvolatile semiconductor memory device

Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to the direction of the linear array, and a parallel portion which runs parallel to the direction of the linear array. The parallel portions are staggered so that longer ones of the parallel portions are adjacent to the shorter ones of the parallel portions, instead of simply being arranged from longest to shortest. In one embodiment, the longer half of the parallel portions decrease in length across the series of parallel portions, while the shorter half of the parallel portions increase in length. In another embodiment, successively longer/shorter parallel portions alternate sides of the series.

Systems and methods for wiring circuit components

A semiconductor device comprises a first transistor and a potential generator circuit. The first transistor has a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semiconductor region. The first and second semiconductor regions are supplied with first and second prescribed potentials, respectively. The potential generator circuit generates the first prescribed potential. The potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential. The potential generator circuit outputs the second power supply potential when the second power supply potential is higher than a predetermined potential, and the first power supply potential when the second power supply potential is lower than the predetermined potential.

Selective switching of a transistor's back gate potential

In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.

Semiconductor memory device of shared sense amplifier system

The control voltage .phi.1 outputted by the control voltage generating circuit 1 is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor P1, but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage .phi.1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor P4 of a low-voltage operating output section 6 operative only at a voltage lower than a predetermined value. The transistor P2 of a full-voltage operating output section 5 of the output circuit is always operative on the basis of the control signal .phi.H of the data output control circuit 3. When the external supply voltage is low below the predetermined value, the transistor P4 is perfectly turned on, so that the conductance thereof increases. In the semiconductor integrated circuit device operative on the basis of a plurality of supply voltages, it is possible to prevent the operation margin from being reduced near the switching point of the gate voltages of the driving transistors and the data output transistors.

Semiconductor integrated circuit device with output circuit

Semiconductor integrated circuit device with data output circuit

A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.

Growing community of inventors

Yokohama, Japan

Eiichi Makino