Kabushiki Kaisha Toshiba

International Business Machines Corporation

Eiichi Hosomi

Chiaki Takubo

Hiroshi Tazawa

Koji Shibasaki

Yasuhiro Koshio

Hiroshi Funakura

Yuichi Goto

Masatoshi Fukuda

Yoichi Hiruta

Naohiko Hirano

Kazuhide Doi

Junya Nagano

Takashi Okada

Atsushi Kurosu

Mitsuru Oida

Tetsuya Nagaoka

Osamu Yamagata

Kaoru Kawai

Kazuhito Higuchi

Susumu Obata

Takashi Arai

Yasuhiro Yamaji

Paul Marian Harvey

Eiji Takano

Atsushi Murakawa

Ryouichi Miyamoto

Masafumi Sugimoto

Kazumi Takahashi

Chiaki c/o Intellectual Property Division Takubo

Hiroshi c/o Intellectual Property Division Tazawa

Koji c/o Intellectual Property Division Shibazaki

A semiconductor device includes a semiconductor substrate provided with a predetermined element and having wirings formed on its main surface connected to back wirings by a plurality of through silicon vias (TSVs), and a conductive cover which covers the main surface of the semiconductor substrate. The semiconductor substrate and the conductive cover are bonded to each other with a conductive bonding member. The TSV bonded to the conductive cover with the conductive bonding member is connected to an external electrode pad to which a ground potential is supplied.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a package substrate, a semiconductor package, a first semiconductor chip and a first bonding wire. The package substrate has a first pad on a first principal surface. The semiconductor package is mounted on the first principal surface of the package substrate. The semiconductor package contains a semiconductor chip and has a second pad. The first semiconductor chip is mounted on the semiconductor package. The first bonding wire is connected between the first pad and the second.

Semiconductor device including semiconductor package

Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell.

Semiconductor device with interface circuit and method of configuring semiconductor devices

Systems, methods and apparatuses for low noise power distribution networks for use with semiconductor devices are disclosed. Embodiments of these systems and methods provide a power distribution network comprising a set of individual power distribution networks, each of the individual power distribution networks operable to provide power to a corresponding functional block of the semiconductor device. These individual power distribution networks may be coupled through capacitors between the power supplies or grounds of each individual power distribution network, such that the individual power distribution networks are coupled in a manner operable to pass AC current between them.

System and apparatus for power distribution for a semiconductor device

Systems and methods for a structure for a package substrate for use in a semiconductor package are disclosed. Package substrates formed according to the systems and methods of the present invention may exhibit improved signal integrity and quality. In order to achieve this increase signal integrity, these systems and methods may endeavor to obtain equalization, or matching, of impedances in signal traces in or on the package substrate by removing material from one or more layers of a package substrate in a region of high signal density. Removing material from these layers may serve to increase the impedance of a signal trace within a region of high signal density such that the impedance of the signal trace with the region of high signal density is substantially matched to the impedance of the signal trace outside the region of high-signal density.

Method and system for an improved package substrate for use with a semiconductor package

Systems and methods for a structure for a power distribution network intended to distribute power from a PCB to a semiconductor device on a package. These improved power distribution networks may reduce current crowding in the BGA balls of a package and may serve to more equitably distribute current through the BGA balls of the package through increasing the impedance of the package or decreasing the impedance of the PCB to which the package is coupled. These systems and methods may increase the impedance of the package through various arrangements of the coupling between BGA balls and planes of the package. By the same token, these systems and methods may decrease the impedance of the PCB coupled to the package by arrangement of the coupling between the PCB and the BGA balls of the package.

Method and system for an improved power distribution network for use with a semiconductor device

Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the 'hot spot' areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.

Systems and methods for reducing simultaneous switching noise in an integrated circuit

Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment of multiple terminals of one or more decoupling capacitors to a single pad. These pads and pad openings can be arranged according to the type of decoupling capacitor employed, allowing a greater total pad area to be utilized in conjunction with a set of pad openings, while simultaneously allowing the multiple pad openings on the pad to be placed closer together, reducing the ESL and ESR of the path between the semiconductor and the decoupling capacitors, increasing the mechanical reliability of the semiconductor package and allowing a higher density of decoupling capacitors to be coupled to a given area.

Method and system for a pad structure for use with a semiconductor package

An exemplary embodiment of the present invention described and shown in the specification and drawings is a semiconductor packaging apparatus that includes a first substrate for coupling to an electronic component, and a second substrate for accommodating the electronic component coupled to the first substrate.

Semiconductor packaging apparatus

A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

Semiconductor package and method of manufacturing the same

An exemplary embodiment of the present invention described and shown in the specification and drawings is a substrate that has lattice points and interstitial points. The substrate includes a surface, a plurality pads located on the surface at interstitial points, and a plurality of vias located in the substrate only at lattice points.

Organic substrate for flip chip bonding

A semiconductor device comprises a memory unit, a selecting signal terminal, and an identifying unit. The selecting signal terminal receives a memory unit selecting signal which is commonly transmitted to a plurality of memory units. The identifying unit distinguishes the memory unit from other memory units on the basis of the memory unit selecting signal, and includes an identifier generating circuit and a memory unit selecting circuit. A plurality of semiconductor devices are laid one over after another, thereby constituting a semiconductor module.

Semiconductor device including memory unit and semiconductor module including memory units

A semiconductor device includes a bonding layer which consists of an intermetallic compound and is positioned between a first electrode and a bump electrode. The bump electrode is mainly made of Au. The intermetallic compound of the bonding layer consist of Au of the bump electrode and a low melting metal.

Growing community of inventors

Kawasaki, Japan

Eiichi Hosomi