Mitsubishi Denki Kabushiki Kaisha

Eiichi Arima

Takeo Muragishi

Akira Nishimoto

Shinichi Jintate

Kazutoshi Oku

Kazuo Sudo

A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.

Electrical erasable and programmable read-only memory and manufacturing

A method of making a non-volatile semiconductor memory device including a memory transistor of a dual gate structure in a memory cell adapted for storing memory information. A first gate insulating layer, a first electronically conductive layer and a second gate insulating layer are formed on the main surface of semiconductor substrate. An etching mask is formed on a third insulating layer formed on the semiconductor substrate. The third and second insulating layers are patterned by etching using a first etching technique while the conductive layer is patterned using a different etching technique to form a gate electrode narrower than the third insulating layer. Impurity ions are implanted diagonally into the main surface of the semiconductor substrate using the patterned third insulating layer at first gate electrode as masks.

Method of manufacturing MDS memory device having a LDD structure and a

A non-volatile semiconductor memory device includes a memory transistor of a dual gate structure in a memory cell adapted for storing memory information. The transistor includes a floating gate and a control gate insulated by an interlayer insulating layer having a laminated structure of silicon oxide and silicon nitride films. The nitride film of the interlayer insulating layer has a visor-like portion protruding from and overlying a portion of the lateral surface of the floating gate. The transistor further is comprised of impurity regions in a so-called LDD structure.

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Hyogo, Japan

Eiichi Arima