Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Fujitsu Corporation

Tanaka, Akira

Takahashi, Eietsu

Sawada, Hisashi

Wakatsuki, Noboru

Takoshima, Takehisa

Nagatani, Shinpei

Yamada, Fumiaki

Eietsu Takahashi

Yasuhiro Shiino

Koki Ueno

Shigefumi Irieda

Kenri Nakai

Daisuke Kouno

Takashi Kobayashi

Akira Tanaka

Yuji Takeuchi

Masaki Kondo

Yoichi Minemura

Tatsuo Izumi

Masashi Yoshida

Shinpei Nagatani

Daisuke Hagishima

Hisashi Sawada

Manabu Sakaniwa

Takehisa Takoshima

Nobushi Matsuura

Koji Kato

Yuji Kojima

Noboru Wakatsuki

Makoto Ohashi

Fumiaki Yamada

Masuji Sato

Toshito Hara

Masao Tanaka

Minoru Terashima

Keisuke Terada

A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Nonvolatile semiconductor memory device

A semiconductor storage device includes a memory cell and a control circuit configured to, upon receipt of a command, acquire a first temperature measured by a temperature sensor, and perform an operation corresponding to the command using a parameter corrected based on temperature. When the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature. When the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.

Semiconductor storage device, method of controlling semiconductor storage device, and memory system

According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.

Semiconductor memory device applying different voltages to respective select gate lines

A memory system includes a nonvolatile memory which includes a memory cell array, and a memory controller which includes a first ECC circuit, and a second ECC circuit having an error correction capability higher than that of the first ECC circuit, and is configured to perform ECC operation on data read from the nonvolatile memory using the first ECC circuit and the ECC circuit. During the ECC operation, the first ECC circuit corrects an error in first read data which is read out of the nonvolatile memory. The memory controller determines whether the hard error occurs in the memory cell array in a case where the first ECC circuit is unable to correct the error. In a case where the hard error occurs, the second ECC circuit performs error correction using second read data that excludes a bit where the hard error occurs.

Memory system

Electrically-rewritable nonvolatile semiconductor memory device

Growing community of inventors

Yokohama, Japan

Eietsu Takahashi