Intel Corporation

Ehud Cohen

Yaniv Fais

Tomer Schwartz

Lev Faivishevsky

Amitai Armon

Jacob Subag

Uzi Sarel

Yahav Shadmiy

Shlomo Raikin

Tomer Bar-On

Jeremie Dreyfuss

Gal Leibovich

Amit Bleiweiss

Oleg Margulis

Zeev Sperber

Raanan Sade

Gad Shlomo Sheaffer

Michael Behar

Vadim Bassin

Julius Yuli Mandelblat

Itamar Ben-Ari

Geeyarpuram N Santhanakrishnan

Guy Jacob

Robert Valentine

Mohan J Kumar

Michael Mishaeli

Ganapati Srinivasa

Theodros Yigzaw

Doron Orenstein

Jose Andy Vargas

Hisham Shafi

Gabi Malka

Gal Novik

Guy Peled

Elmoustapha Ould-Ahmed-Vall

Mark Jay Charney

Christopher J Hughes

Eliezer Weissmann

Edward Thomas Grochowski

Ronny Ronen

Milind Baburao Girkar

Boris Ginzburg

Stanislav Shwartsman

Deborah T Marr

Jonathan D Pearce

Asit K Mishra

Jesus Corbal San Adrian

Benny Eitan

Ron Gabor

Zeev Offen

Larisa Novakovsky

Moshe Maor

Doron Orenstien

Adnan M Agbaria

Karthikeyan Karthik Vaithianathan

Daniel David Ben-Dayan Rubin

Karthikeyan Vaithianathan

Dmitri Vainbrand

Michelle J Moravan

Ashutosh Parkhi

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

A convolutional neural network (CNN) accelerator, including: a CNN circuit for performing a multiple-layer CNN computation, wherein the multiple layers are to receive an input feature according to an input feature map (IFM) and a weight matrix per output feature, wherein an output of a first layer provides an input for a next layer; and a mapping circuit to access a three-dimensional input matrix stored as a Z-major matrix; wherein the CNN circuit is to perform an inner-product direct convolution on the Z-major matrix, wherein the direct convolution lacks a lowering operation.

Inner product convolutional neural network accelerator

In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.

Low rank matrix compression

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

Variable precision and mix type representation of multiple layers in a network

A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

Smart memory handling and data management for machine learning networks

In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer.

In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Data element comparison processors, methods, systems, and instructions

Techniques and apparatus for providing graph compression structures for graph information are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, coupled to the at least one processing circuitry, to access graph information comprising a plurality of nodes, define a unique index for each of the plurality of nodes, determine whether each of the plurality of nodes has at least one neighbor node, and generate a graph compression structure comprising an entry for each of the plurality of nodes having at least one neighbor node and an adjacency list comprising an array of neighbor nodes of each entry.

Techniques for information graph compression

Growing community of inventors

Kiryat Motskin, Israel

Ehud Cohen