Infineon Technologies Ag

Other

Universitaet Potsdam

Egor Sogomonyan

Michael Goessel

Michael Gössel

Georg Georgakos

Daniel Marienfeld

Methods and apparatuses relating to error-tolerant memories are provided. In one example embodiment, output signals from at least three memory devices are supplied to an error correction device. The error correction device outputs a corrected data value in such a manner that, when the read data values match, this data value is output and, in at least one state in which the data values do not match, a previously output data value is retained.

Error-tolerant memories

The invention relates to a circuit arrangement, comprising: a functional circuit with m (m=1, 2, . . . ) data inputs and n (n=1, 2, . . . ) data outputs for processing at least one m-dimensional binary data input (x, . . . , xm) to form an n-dimensional data output (y, . . . , yn), wherein the functional circuit comprises at least one combinatorial circuit part, at least two registers with a word length k (k=1, 2, . . . ; k&#x2266;n) which are coupled to at least some of the n data outputs of the functional circuit in order to store output values (y=y, . . . , yk; y'=y&#x2032;, . . . , y&#x2032;k) which are duplicated with respect to one another or are duplicated with bit-by-bit inversion with respect to one another, said output values being derived from the n-dimensional data output (y, . . . , yn) of the functional circuit, at least one corrector with an input word length 2k and an output word length k, which is coupled to data outputs of the at least two registers and supplies a k-dimensional corrected data output (y[k](korr)=y(korr), . . . , yk(korr)), and an error detection circuit for detecting errors during operation of at least one of the aforementioned circuit elements: the functional circuit, the at least two registers and the corrector.

Circuit arrangement

A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E, . . . , En for inputting n (n&#x2267;2) information bits x, . . . , xn and m binary outputs for outputting m (m&#x2267;1) check bits c, . . . , cm. The combinational circuit is configured for realizing a Boolean function ci=fi(xi, . . . , xini) for i=1, . . . , m at the i-th output for determining a check bit ci, wherein the set {xi, . . . , xini} at the ni information bits that determine the check bit ci is a subset of all n information bits {x, . . . , xn}. The combinational circuit is furthermore configured for realizing a first Boolean function f(x, . . . , xn) of the form c=f(x, . . . , xn)=f(x, x) XOR f(x, x) XOR . . . XOR fk(x(n&#x2212;1), xn) at a first output for outputting a first check bit c, wherein nis an even number where n&#x2267;2 and 2 k=nand the Boolean functions f(x, x), . . . , fk(x(n&#x2212;1), xn) are in each case nonlinear Boolean functions of two variables which can be realized by logic gates having two inputs and one output, wherein the logic gates each have a controlling value c, . . . , ck

Circuit arrangement and method for error detection and arrangement for monitoring of a digital circuit

The invention relates to a circuit for comparing two n-digit binary data words x[1](t), . . . , x[n](t) and x'[1](t), . . . , x&#x2032;[n](t), which in the error-free case are either identical or inverted bit-by-bit with respect to each other, with a series connection of a combinatorial circuit for implementing a first combinatorial function, a controllable register and a combinatorial circuit for implementing another combinatorial function.

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Potsdam, Germany

Egor Sogomonyan