Schlumberger Technologies, Inc.

Schlumberger Technology Corporation

Egbert Graeve

Burnell G West

Rodolfo F Garcia

David K Cheung

Teck Chiau Chew

In a tester for testing circuits, apparatus and methods for acquiring waveform data from a circuit under test. While a test program is being run by the tester, waveform acquisition strobe events are generated for application to a terminal of a circuit under test. A measurement circuit receives the waveform acquisition strobe events and applies each strobe event to the terminal of the circuit and generates result signals representing the result of applying the strobe events to the terminal. A capture memory receives and stores result signals generated by the measurement circuit.

Tester having event generation circuit for acquiring waveform by

Apparatus and methods providing pattern chaining and looping in a circuit tester. The tester has a pattern data memory for storing multiple patterns and for storing a pattern chaining definition. Each pattern has pattern data for one or more test vectors. The pattern chaining definition specifies (i) a sequential order for the patterns and (ii) a location in the pattern data memory of each of the patterns. When the tester executes a functional test, the pattern chaining definition is read from the pattern data memory and used to locate each of the patterns, and the pattern data of each pattern is read to provide a test vector for each test period of the functional test. In another aspect, both a pattern program including one or more test vectors and a loop definition are stored in the pattern data memory. The pattern program defines an ordering for the test vectors, and the loop definition specifies a loop of test vectors. When the tester executes a functional test that includes the loop, the test vectors of the loop are read an indefinite number of times until a loop ending condition occurs. The first loop test vector of the loop need not be the initial test vector of the pattern program. In another aspect, the tester has chaining control registers including a start address register for pointing to a pattern chaining definition stored in the pattern data memory and a current pattern pointer register for pointing to a current pattern stored in the pattern data memory; a pattern data output sequencer; and a pattern data buffer memory coupled between the pattern data memory and the pattern data output sequencer.

Providing test vectors with pattern chaining definition

A test system, for testing circuits, having two operating modes, a normal mode and an accelerated mode. The test system has a first start memory, a second start memory, a first sequence memory, and a second sequence memory. The start memories provide sequence memory addresses for addressing the sequence memories, and the sequence memories provide event sequences in response to sequence memory addresses. If operating in normal mode, the start memories are electronically coupled (switched) to provide a single sequence memory address to both sequence memories. If operating in accelerated mode, the start memories are electronically coupled so that the first start memory provides a first sequence memory address to the first sequence memory and the second start memory provides an independent second sequence memory address to the second sequence memory. In particular embodiments, the first and second start memories are of the same size, the first and second sequence memories are of the same size, and the sequence memories produce a word including at least two events in response to a sequence memory address. In a further embodiment, the test system has three operating modes: normal, accelerated, and double-accelerated. For the double-accelerated mode, four start memories and four sequence memories are provided.

Accelerated mode tester timing

A Device Under Test ('DUT') is monitored to determine when a test stops due to failure, completion, or otherwise. A series of signal stimulus in the form of a maintain active signal are applied to the DUT after the test has stopped. This protects devices that need continuous functional stimulus while connected to a power source. Upon the resumption of the test, the maintain active signal stimulus is synchronously replaced with an input test signal stimulus.

Apparatus for maintaining stimulation to a device under test after a

A number of local sequencers, one for each pin of the device under test is disclosed. Each local sequencer is provided with a global clock, a global time zero signal indicating the clock edge for referencing the start of a test, and a period vernier indicating an offset from the clock for the start of the test period. Each local sequencer uses this information to generate its own test events referenced to the test period with individual calibration delays factored in locally. Each local sequencer is individually programmable so that different sequencers can provide different numbers of events during the same test period.

Event sequencer for automatic test equipment

A plurality of 'pin slice' circuits, each associated with a separate pin of the device under test (DUT). Each pin slice circuit contains its own memory and registers and circuitry for generating the necessary test signals. Test data is loaded into the individual pin slice circuits in a vertical word fashion, such that all of the bits of the vertical word correspond to the individual pin, allowing the characteristics of an individual pin test sequence to be varied independently of the other pins. A participate memory is used to select different groupings of the pin slice circuits which are to be programmed in parallel when a group of pins are to receive the same test signals. Separate enable signals to the various stages of the pin slice circuits allow different aspects of the test pattern to be also varied independently.

Automatic test equipment system using pin slice architecture

A data stream smoothing circuit wherein a FIFO memory receives data from the DRAM, and a memory status circuit provides a memory-full status signal when the FIFO memory contains a selected amount of data from the DRAM. A refresh timer generates a refresh request signal whenever DRAM refresh should be performed. When the refresh request signal is generated, a refresh control circuit refreshes a row of data in the DRAM upon occurrence of the next memory-full status signal.

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Los Altos, CA, United States of America

Egbert Graeve