Intel Corporation

Kla Tencor Corporation

Tahoe Research, Ltd.

Efraim Rotem

Eliezer Weissmann

Doron Rajwan

Nir Rosenzweig

Nadav Shulman

Alon Naveh

Avinash N Ananthakrishnan

Krishnakanth Venkata Sistla

Guy M Therien

Yoni Aizik

Ankush Varma

Anil Aggarwal

Hisham Abu Salah

Paul S Diefenbaugh

Dorit Shapira

Jeremy J Shrall

Ryan Donovan Wells

Michael Mishaeli

Alexander Gendler

James G Hermerding, Ii

Jason W Brandt

Ronny Ronen

Eric DiStefano

Lev Finkelstein

Barnes Cooper

Boris Ginzburg

Inder M Sodhi

Russell Jerome Fenger

Andrew D Henroid

Jorge Pedro Rodriguez

Stephen H Gunther

Gal Leibovich

Amnon Manassen

Eric C Samson

Eugene Gorbatov

Daniel Kandel

Vivek Garg

Ian M Steiner

Ashish V Choubal

Daria Negri

Ohad Bachar

Michael Zelikson

Joel L Seligson

Alexander Svizher

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Yung-Ho Alex Chuang

Vladimir Levinski

Andrew V Hill

Eyal Fayneh

Ahmad Yasin

Tsvika Kurts

Chee Lim Nge

Julius Yuli Mandelblat

Tal Kuzi

Yuval Yosef

Baruch Chaikin

Zeev Sperber

Dan Baum

David A Koufaty

Rajiv K Mongia

Tod F Schiff

Alexander Uan-Zo-Li

Rakesh Kumar

Scott D Hahn

Zhongsheng Wang

Michael A Rothman

Mohan J Kumar

Varghese George

Sanjeev S Jahagirdar

David I Poisner

Raanan Sade

Ohad Falik

Ittai Anati

Ron Gabor

Dheeraj R Subbareddy

Robert E Gough

Stanislav Shwartsman

Sarathy Jayakumar

Ganapati Srinivasa

Igor Yanover

Mark Doran

Asit K Mallick

Lily Pao Looi

Noam Sapiens

Jose Andy Vargas

Larisa Novakovsky

Shaun M Conrad

Aamer Jaleel

Guy Cohen

Reid James Riedlinger

Douglas Raymond Moran

Alexander Lyakhov

Rajshree Chabukswar

Paolo L Narvaez

Neelam Chandwani

Ernest Knoll

Vadim Bassin

Avi Mendelson

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling.

Device, method and system to provide thread scheduling hints to a software process

In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

Multi-level loops for computer processor control

In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

Processor having accelerated user responsiveness in constrained environment

A hardware and/or software (e.g., a controller and/or firmware or software) that monitors a remaining capacity of a battery and adjusts a continuum of system performance settings ranging from best performance to best energy efficiency. The controller starts with best performance setting (at the expense of energy efficiency), and then the controller gradually shifts toward energy efficiency setting (at the expense of performance) when a battery usage exceeds a pre-defined drain rate (e.g., there is a deficit in the battery remaining capacity until the next charge). The controller reverts from energy efficiency setting towards high performance setting when the battery drain rate or discharge rate slows down (e.g., there is a surplus in the battery remaining capacity until the next charge).

Predictable battery power management apparatus and method

Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Current control for a multicore processor

A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

System, apparatus and method for loose lock-step redundancy power management

An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

Power management based on real time platform power sensing

Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Apparatuses, methods, and systems for hardware control of processor performance levels

Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

Application priority based power management for a computer device

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

Leakage degradation control and measurement

Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

Multi-level CPU high current protection

Growing community of inventors

Haifa, Israel

Efraim Rotem