International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Other

Adeia Semiconductor Bonding Technologies Inc.

Tessera LLC

Effendi Leobandung

Tenko Yamashita

Devendra K Sadana

Ning Li

Cheng-Wei Cheng

Veeraraghavan S Basker

Kevin K Chan

Ghavam G Shahidi

Chun-chen Yeh

Renee Tong Mo

Jean-Olivier Plouchart

Theodorus E Standaert

Tak H Ning

Babar Ali Khan

Xinhui Wang

Sivananda K Kanakasabapathy

Russell Alan Budd

Wilfried Haensch

Brent A Wacaser

Huilong Zhu

Paul Michael Solomon

Dae-Gyu Park

Kuen-Ting Shiu

Pranita Kerber

Min Yang

Dominic Joseph Schepis

Jin Cai

William Joseph Gallagher

Andres Bryant

Huiming Bu

Chun-Chen Yeh

Pouya Hashemi

Junli Wang

Seyoung Kim

Dieter F Wendel

Alexander Reznicek

Soon-Cheon Seo

Amlan Majumdar

Tze-Chiang Chen

Lukas Czornomaz

Jerome Brett Lasky

Jean Fompeyrine

Ruilong Xie

Stephen W Bedell

Fee Li Lie

Jingyun Zhang

Chung-Hsun Lin

Werner A Rausch

David V Horak

John Ulrich Knickerbocker

Robert J Gauthier, Jr

Keith E Fogel

Guy M Cohen

John J Ellis-Monaghan

Vijay Narayanan

Michael A Guillorn

Jed Hickory Rankin

Terence B Hook

Isaac Lauer

Christian Lavoie

James William Adkisson

Kirk David Peterson

Fei Liu

Jeffrey Bowman Johnson

Jeng-Bang Yau

Hsueh-Chung Chen

Qingqing Liang

Brian Joseph Greene

Deborah A Neumayer

Huicai Zhong

Xiao Lin Sun

Dennis Merton Newns

James Douglas Warnock

Wesley Charles Natzle

Kevin W Brew

Byeong Yeol Kim

David M Dobuzinsky

Philip Joseph Oldiges

Bruce Bennett Doris

Lawrence Alfred Clevenger

Nicolas J Loubet

Oleg Gluschenkov

Haining S Yang

Josephine B Chang

Dureseti Chidambarrao

Shom Ponoth

Julien Frougier

Hong He

Leland Chang

Andrew Mark Greene

Yann Mignot

Ravikumar Ramachandran

Laertis Economikos

Dirk Pfeiffer

Tymon Barwicz

Meikei Ieong

Gauri V Karve

Albert Manhee Chu

Anthony I Chou

Tayfun Gokmen

Various methods and structures for fabricating a semiconductor structure with vertical vias interconnecting BEOL metallization layers. A first BEOL metallization layer includes a first metallization contact. A second BEOL metallization layer is disposed on the first BEOL metallization layer. The second BEOL metallization layer includes a second metallization contact. A dielectric layer is vertically interposed between the first and second metallization layers. A first vertical via interconnects, through the dielectric layer, the first and second metallization contacts. In the first vertical via, a phase change material non-volatile memory (PCM) is vertically interposed between an upper electrode and a lower electrode. The lower electrode is electrically connected to the first metallization contact. The upper electrode is electrically connected to the second metallization contact.

Multi function single via patterning

An aggregate die comprises a substrate, a first sub die, and a second sub die. The substrate comprises a surface with a first set of substrate alignment guides and a second set of substrate alignment guides. The first sub die comprises a first set of sub die alignment guides that interface with the substrate alignment guides in the first set of substrate alignment guides. The second sub die comprises a second set of sub die alignment guides that interface with substrate alignment guides in the second set of substrate alignment guides.

Processor die alignment guides

An approach for validating a logic key in an IC (integrated circuit) is disclosed. One approach includes an IC comprising of key input circuit couple to a fuse check circuit; charge pump circuit coupled to the fuse check circuit and a switch matrix; and one or more antifuse circuit connected to the switch matrix. Another approach comprises of a method including, inputting a secret key by a user; determining status of one or more antifuse circuit; validating the secret key; in responsive to the secret key not matching an original secret key, determining whether antifuse threshold has been reached; in responsive to determining that the antifuse threshold has been reached, disabling the IC; in responsive to the secret key matching the original secret key, enabling the IC; and in responsive to determining that the antifuse threshold has not been reached, activating the antifuse circuit.

Logic circuit locking with self-destruct

A security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches are set causing the plurality of programmable switches to be conductive. Reset pulses are applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.

Integrated circuit security using programmable switches

A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10Ω·m and has a thickness of greater than or equal to 1 μm. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.

X-ray shielding structure for a chip

3D NOR flash memory devices having vertically stacked memory cells are provided. In one aspect, a memory device includes: a word line/bit line stack with alternating word lines and bit lines separated by dielectric layers disposed on a substrate; a channel that extends vertically through the word line/bit line stack; and a floating gate stack surrounding the channel, wherein the floating gate stack is present between the word lines and the channel, and wherein the bit lines are in direct contact with both the channel and the floating gate stack. Techniques for configuring the memory device for neuromorphic computing are provided, as are methods of fabricating the memory device.

Vertical three-dimensional stack NOR flash memory

A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.

Semiconductor structure with different crystalline orientations

Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.

Staircase patterning for 3D NAND devices

A stacked field effect transistor device is provided. The stacked field effect transistor device includes a lower semiconductor channel segment between a first pair of source/drains, and an upper semiconductor channel segment between a second pair of source/drains. The stacked device further includes a gate dielectric layer on the upper and lower semiconductor channel segments, and a first work function material layer on the gate dielectric layer on the lower semiconductor channel segment. The stacked device further includes a first conductive gate fill on the first work function material layer, and a replacement work function material layer on the gate dielectric layer on the upper semiconductor channel segment and the first conductive gate fill, wherein the replacement work function material layer is a different work function material from the first work function material layer. The device further includes a replacement conductive gate fill on the replacement work function material layer.

Stacked field effect transistor devices with replacement gate

The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Secure fingerprinting of a trusted photomask

A circuit for monitoring usage of an active field effect transistor (FET) includes the active FET and a reference FET, formed in a same structure as the active FET. The active FET and the reference FET both are pFET or both are nFET, and are stacked on each other at a common gate. The circuit also includes a differential current sense circuit (DCSC) and a plurality of switches for connecting terminals of the FETs to logic voltage, ground voltage, and/or the DCSC. The DCSC is configured to measure and compare currents through each of the active and reference FETs when a threshold voltage is applied to the common gate.

Transistor usage metering through bias temperature instability monitoring

According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.

Mask fingerprint using mask sensitive circuit

A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.

Co-integrated logic, electrostatic discharge, and well contact devices on a substrate

Techniques for usage metering by bias temperature instability with differential sensing on pairs of matching transistors are provided. In one aspect, a usage metering device includes: at least one metering circuit on a chip, the at least one metering circuit having a pair of matching transistors, and a differential current sense circuit connected to the pair of matching transistors, wherein the pair of matching transistors includes a reference transistor which is unused during regular operation of the chip, and a stressed transistor that is on continuously during the regular operation of the chip, and wherein the differential current sense circuit determines a Vt difference between the reference transistor and the stressed transistor. A method for usage metering and a method of forming a usage metering device are also provided.

Usage metering by bias temperature instability

A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof

Growing community of inventors

Stormville, NY, United States of America

Effendi Leobandung