Vlsi Solution Oy

Tritech Microelectronics, Ltd

Other

Eero Pajarre

Tapani Ritoniemi

Timo Husu

Ville Eerola

Seppo Ingalsuo

Tapio Saramaki

Otto Chrons

Tapio Saram&auml;ki

Mika Hoffren

The invention relates to a method and an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients, and to a method for designing such a filter. The invention comprises a shift register ( ) shifting in the direction of the least significant bit and copying the most significant bit or filling in zero values. The register receives the binary input signal of the filter and has outputs for outputting the content of the desired bit positions. A plurality of bit-serial subtractor and adder elements ( ) multiply the binary input signal by N&plus;1 different tap coefficients by combining output bits of the shift register ( ). The subtractor and/or adder elements form a network wherein at least one element participates in the multiplying operation of at least two different tap coefficients.

Method and arrangement in a transposed digital FIR filter for multiplying a binary input signal with tap coefficients and a method for designing a transposed digital filter

A device (,) for presenting 3D graphics comprises means for defining one or more polygons for objects to be presented, means (,) for bump mapping, which comprises means (,) for storing a bump map and means (,) for fetching the bump map from the bump map storing means (,), and means for defining a direction vector of bump map normal at each vertex of a polygon, and means (,) for rasterizing images on a display device. The device (,) comprises further means (,) for producing an angle value which is used to rotate the direction vector of the bump map.

3D graphics device

The present invention relates to arithmetical computing devices, and especially to a division operation in three-dimensional (3D) graphics. A division f(a,b)=a/b is calculated by an integrated division circuit. In order to decrease the chip area and calculation time needed, the bit width of the divider and the dividend is reduced by preprocessing. Firstly, the scaling factor is searched in basis of the divider. Then both the divider and divident are scaled by the single scaling factor. Division is then done with these shrunk bit vectors.

Apparatus for performing a division operation, especially for

Calculation of a scalar product in a direct-type FIR filter

A pixel processing apparatus receives pixels from an external source (100) and stores them in a storage area (110). A data path (120) performs mathematical operations and tests whether or not a pixel is to be suppressed. For an effective memory access, a control logic (130) provides addresses to the storage area (110). The control logic (130) receives status data from the data path (120), indicating whether or not a pixel is to be suppressed and modifies the status register (140) accordingly. The control logic (130) prevents the data path (120) from performing further operations on a pixel if the status register (140) indicates that the pixel is to be suppressed. Preferably, the control logic suppresses address generation for the location of the pixel in question if said status register (140) indicates that the pixel is to be suppressed.

Method and apparatus for processing picture elements

Decimation filter

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Tampere, Finland

Eero Pajarre