Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Edwin Thaller

Giuseppe Li Puma

Stefano Marsili

Roberto Nonis

Stefan Van Waasen

Nicola Da Dalt

Patrizia Greco

Davide Ponton

Nicola DaDalt

Yanzhong Dai

Andreas Steinschaden

Gernot Zessar

Kameran Azadet

Franz Kuttner

Daniel Gruber

Christian Lindholm

Patrick Torta

Michael Kalcher

James M Yoder

Alan Paussa

Yu-Shan Wang

Ramani Tatikola

Georg Weber

Wee Liew

A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Chip-to-chip interface of a multi-chip module (MCM)

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

Analog-to-digital conversion

A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

Signed-RFDAC architectures enabling wideband and efficient 5G transmitters

Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Multi-output phase detector

Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Oscillator circuit

The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.

Polar transmitter suitable for monolithic integration in SoCs

One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.

Split varactor array with improved matching and varactor switching scheme

One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal.

Digital PLL with automatic clock alignment

Implementations of differential variable capacitance systems are disclosed.

Variable capacitance unit

In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

Circuit with noise shaper

The voltage controlled oscillator (VCO) circuit comprises a tank circuit, a first tuning section comprising first capacitor elements wherein each one of the first capacitor elements is individually utilizable for the tank circuit, and a second tuning section comprising second capacitor elements wherein each one of the second capacitor elements is individually utilizable for the tank circuit and the capacitance of each one of the second capacitor elements is continuously adjustable in a predetermined capacitance range in dependence on a tuning voltage.

Voltage controlled oscillator circuit and a method for configuring a voltage controlled oscillator circuit

A delay stage for a semiconductor device includes at least one delay branch and at least one controllable switching apparatus. The at least one controllable switching apparatus is configured to connect a predefined amount of the at least one delay branch to a supply voltage.

Delay stage, ring oscillator, PLL-circuit and method

A device for extracting a clock frequency underlying a data stream includes means for controlling a controllable oscillator, coarse-tuning means and fine-tuning means, wherein coarse-tuning means responds to a second data pattern present in the data stream and sets the oscillator coarsely based on its length. Fine-tuning means responds to temporally consecutive first data patterns present in the data stream with a higher accuracy in order to perform a fine tuning of the oscillator on the basis of the temporal length between the two first data patterns and on the basis of the number of clock cycles of the controllable oscillator occurring in this temporal length.

Growing community of inventors

Faak am See, Austria

Edwin Thaller