Matsushita Electric Corporation of America

Matsushita Electric Industrial Co., Ltd.

Edwin Robert Meyer

Saiprasad V Naimpally

Hee-Yong Kim

Larry Phillips

Ren Egawa

Richard Sita

Robert T Ryan

Shuji Inoue

Siu-Leong Iu

Ghanshyam Dave

Michael Iaquinto

Edward Brosz

Jereld Pearson

Joseph P O'Hara

A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which decodes an ATSC encoded image and employs a downconversion process to produce a standard definition video signal. The video decoder includes a frequency-domain filter to reduce the resolution of the ATSC encoded signal. The video decoder downconversion system also includes a formatting section having vertical and horizontal filters, as well as resampling processing, to format the decoded and downconverted video image for a particular display and aspect ratio. The decoder senses the display format of the encoded video signal and changes the processing provided by the decoder to produce a standard definition output signal regardless of the display format of the encoded input signal. The system also includes a format converter which may be programmed to use a plurality of methods to convert the aspect ratio of the input signal for display on a display device having a different aspect ratio. In one mode, the system sequences through the possible methods to allow the user to select one method.

HDTV downconversion system

An HDTV down conversion system including apparatus for forming a set of low resolution down-sampled pixel values corresponding to a current frame of a video signal from a set of low resolution pixel values corresponding to a residual image of a current frame of the video signal and from a set of down-sampled low resolution pixel values corresponding to reference frames of the video signal. The apparatus includes a memory for storing the set of down-sampled low resolution pixel values. An up-sampling processor receives from the memory and uses Lagrangian interpolation to convert the set of down-sampled low resolution pixel values corresponding to the reference frame of the video signal into a set of up-sampled low resolution pixel values corresponding to the reference frame of the video signal. A summing processor adds the set of low resolution pixel values corresponding to the residual image of the current frame of the video signal to the set of up-sampled low resolution pixel values corresponding to the reference frame of the video signal to form a set of low resolution pixel values corresponding to the current frame of the video signal. A decimating processor deletes selected ones of the set of low resolution pixel values corresponding to the current frame to generate the set of low resolution down-sampled pixel values corresponding to the current frame of the video signal.

Upsampling filter for a down conversion system

A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which, when the decoder is operated in a first mode, decodes a Main Profile, High Level (MP&commat;HL) image to produce a high-definition video output signal and decodes a Main Profile, Main Level (MP&commat;ML) signal to produce a standard definition video signal. In addition, when the decoder is operated in a second mode, circuitry is used which generates a standard definition image from the MP&commat;HL signal. The video decoder includes a frequency-domain filter to reduce the resolution of the MP&commat;HL signal when the decoder is operated in the second mode.

MPEG decoder providing multiple standard output signals

A video down conversion system compliant with the Advanced Television Systems Standard (ATSC) includes a decoder which decodes a Main Profile, High Level (MP&commat;HL) image and employs a downconversion processor to produce a standard definition video signal. The system stores a subsampled image in order to reduce memory requirements and employs an upsampling filter to generate reference image data from the stored. subsampled image. The reference image data spatially correspond to the image data produced by the video decoder before it is subsampled. The upsampling filter uses different filter coefficients based on the subsampling phase of the stored image and the half-pixel indicator in the motion vector which is used to locate the downsampled reference image data in the stored subsampled image.

Upsampling filter and half-pixel generator for an HDTV downconversion system

A discrete cosine transform domain (DCT) filter for lowpass filtering a high resolution encoded video image represented as frequency-domain coefficient values, such as macroblocks, before decimation of the video image in the spatial domain. The DCT filter masks or weights the DCT coefficients of the video image macroblocks before processing by an inverse DCT. The filter may be implemented as a block mirror filter in the frequency domain, and the filter values may be combined with the IDCT coefficient values. Original motion vectors of the high resolution encoded video image are translated because low resolution reference images used by the decoder are not equivalent to the original high resolution images. Therefore, motion vectors are scaled to retrieve low resolution prediction blocks which are up-sampled to generate the original pixel and half-pixel values in the spatial domain. The up-sampled prediction block is added to the DCT filtered inverse-DCT transformed pixel values if the current macroblock is part of a non-intraframe encoded image. After motion compensation processing of the original macroblock, the reconstructed macroblock in the lower resolution is decimated accordingly.

Frequency domain filtering for down conversion of a DCT encoded picture

A transport decoder 110, for receiving and processing a transport data stream using MPEG-2 formats, includes connections to a physical layer channel interface (channel interface) 112, a buffer memory 114, a host microprocessor 116, audio and video decoders 118/120, and clock signal circuitry 122. Upon receipt of a discontinuity indicator, the transport packet headers are parsed and transport packet payloads are stored in memory. Subsequently, upon receipt of a next program counter reference (PCR) value, a counter is loaded with the received program counter reference value. Next, the data stored in memory is searched for a time stamp and, when one is found, the time stamp is retrieved. Finally, a timer interrupt is set for a point in time approximately one frame time before the time stamp value, and, when the timer interrupt occurs, the program counter reference value is sent to the decoders, thereby providing sufficient time for the decoders to process data.

System and method for updating a system time constant (STC) counter

A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value. The count value is compared to a succession of externally supplied system clock reference (SCR) values to generate a phase difference signal that is used to adjust the frequency of the signal produced by the DPLL. In addition, the DPLL is aligned in phase by substituting respective portions of the SCR value for the count value developed by the DPLL and for the accumulated phase value used by the DPLL.

MPEG video decoder having a high bandwidth memory

A variable length decoder for decoding a variable length code. The variable length decoder includes a first look-up table for receiving and decoding the most significant bits of the variable length code and for producing a first decoded code corresponding to the most significant bits. The first look-up table means also for outputs a conversion signal. In addition, a second look-up table is provided for receiving and decoding the least significant bits and for producing a second decoded code corresponding to the least significant bits. The first look-up table and the second look-up table decode the most significant bits and the least significant bits at substantially the same time. The decoded output of the look-up tables is provided to a selector. The selector selects the first decoded code or the second decoded code based upon the conversion signal.

Variable length code decoder for simultaneous decoding the most

A method of splicing two compressed video signals which have been encoded according to the standard adopted by the Moving Picture Experts Group (MPEG) determines an amount of null information that is to be inserted between the two video signals in order to ensure that an input buffer of an MPEG decoder does not overflow after receiving the spliced video signals. The method allows a splice to occur after any access unit (picture) in the first compressed video signal. The amount of null information is determined from the data rates of the first and second compressed video signals and the amount of new data which is provided to the buffer before the data is retrieved from the buffer for both the first and second video signals. The video signals are spliced by inserting the null information, as sequence stuffing bits into a buffer immediately after the selected picture in the first video signal. The second video signal is transmitted to the buffer immediately after these stuffing bits.

Method of splicing MPEG encoded video

The present invention is embodied in a decoder for a video signal encoded according to the standard proposed by the Moving Pictures Expert Group (MPEG) of the International Standards Organization (ISO). This decoder employs four sets of processors, each set containing three processors that operate concurrently to decode the MPEG-2 video signal. A variable length decoder processes the input stream to decode the variable length encoded data. The operations performed by this decoding processor change depending on the type of data being decoded. These changes are implemented using a master Digital Signal Processor (DSP) which is programmed according to the MPEG-2 syntax. The data decoded by the VLD processor is either video data or control data. The control data is divided into two types, control data needed to reproduce the image and control data that describes the bit-stream. The control data needed to decode the image is passed to a control DSP while the control data which describes the bit-stream is passed to the master DSP. To ensure that the entire system can operate with sufficient speed to decode an image in real time, this group of three processors is duplicated four times in the system. Each set of processors operates in parallel and handles digital data representing a distinct portion of the final high definition television image.

Variable length data decoder for use with MPEG encoded video data

A system and method for filtering a digital signal having a relatively high data rate uses circuitry which operates at a lower data rate. The filter includes an input section which receives the input signal and which divides the input signal into a plurality of contiguous segments. The system also includes a first filter which receives samples representing one of the plurality of segments and adjacent samples from the next contiguous one of the segments and which filters all of the received samples to produce a first filtered signal. A second filter receives samples of the next contiguous segment and filters those samples to produce a second filtered signal. The filtered signals are combined by providing the samples of the second filtered signal immediately after the samples of the first filtered signal to produce a filtered output signal. The invention also relates to using respective timing signals associated with the segments to determine when the samples of the first and second filtered signals are provided.

HDTV raster converter and interpolation filter with section overlap

Apparatus for selecting a block of data in a previous frame to be used as a predicted block for a given block in a current frame in a system that reduces the bit rate by codifying the difference between the predicted block and the given block in a given manner by deriving the differences between the given block in the current frame and a plurality of blocks in the previous frame and selecting as the predicted block that block for which the codification of its differences with the given block requires the least number of bits. The apparatus can also select a predicted block from a number of blocks selected in accordance with ABD or SBD techniques.

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Bensalem, PA, United States of America

Edwin Robert Meyer