Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Edwin P Fisher

Robert B Johnson

Alvan W Ng

James W Keeley

Chester M Nibby, Jr

John L Curley

Edward R Salas

Daniel A Boudreau

Ralph G Schuberth

Victor L Quattrini

Paul S Feldman

A multilayer printed circuit memory board is designed and constructed so that the top and bottom layers contain repetitive integrated circuit (IC) chip component hole/pad and interconnection line patterns which are mirror images of one another. The board uses surface mounted techniques in which the integrated chip components of the memory array are mounted and soldered to both sides of the board thereby doubling the density or capacity of the memory board. The integrated circuit memory chips, mounted on the top and bottom of the board, are aligned with each other for sharing common holes or vias in which logically equivalent input signal connections are exchanged in a manner for reducing the number of holes and length of connective wiring.

Surface mounted multilayer memory printed circuit board

A memory subsystem couples to a bus in common with and proceses memory requests received therefrom. The subsystem includes a single addressable memory module unit or stack having a number of word blocks of dynamic random access memory (DRAM) chips mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. Chip select circuits preselect a pair of blocks of RAM chips from the stack. Timing circuits generate a plurality of sequential column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the sequential read out of a pair of words from the preselected blocks of the single word wide module into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out in sequence providing a double fetch capability without any loss in system performance.

Computer memory apparatus

A memory subsystem couples to a bus in common with a central processing unit and processes memory requests received therefrom. The subsystem includes a number of addressable memory module units or stacks each having a number of word blocks of dynamic random access memory (DRAM) chips arranged in one of two subsystem configurations and mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. The configurations correspond to a common stack arrangement which provides double the normal amount of density and an adjacent stack arrangement of normal density. As a function of an input density signal, chip select circuits preselect a pair of blocks of RAM chips from a common stack or pair of adjacent stacks. Timing circuits generate a plurality of sequential column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the read out of a pair of words from the preselected blocks of a single stack or adjacent stacks in tandem into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out into the data registers in the same sequence providing a double fetch capability without any loss in system performance.

A memory board can be assembled with one, two or more rows of memory chips to provide a corresponding number of different memory capacities for expanding the capacity of main memory which resides on a basic logic board containing the processing units and other units of a system. The memory board includes a programmable read only memory (PROM) circuit which receives as inputs from the basic logic board a predetermined address portion of each memory address together with memory refresh and timing signals. The PROM circuit is coded in a predetermined manner for generating at its output terminals row address select (RAS) pulse output signals to a row or block of memory chips designated by the predetermined address portion. The pulse widths of the output signals are established by the timing signal applied to an enabling terminal of the PROM.

Memory timing and control apparatus

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.

Memory identification apparatus and method

The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detection signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free thereby gracefully degrading cache operation.

Multilevel cache system with graceful degradation capability

Tri state logic gates in series are disclosed for permitting the latching of information from a first circuit by enabling a second circuit at the time information from the first circuit becomes valid. At the start of the memory cycle the second circuit is disabled and the first circuit is enabled. The data in the memory will appear at the output of the memory circuit to be delivered to the computer. Data is latched and retained on the data output bus by enabling the second circuit which assumes the level that appears on its input when enabled. The first circuit may then be disabled to permit it to carry out other operations.

Transparent tri state latch

Apparatus and method for generating substrate bias for the refresh apparatus of volatile memory elements associated with data processing units. A refresh oscillator in the refresh apparatus is utilized to drive a chopper circuit or high level driver in combination with a rectifier network for obtaining raw negative voltage. The raw voltage is filtered and adjusted to the correct value on the metal oxide semiconductor (MOS) memory board and distributed to each random access memory (RAM).

Substrate bias voltage generated from refresh oscillator

An apparatus is disclosed which comprises an improved voltage driver circuit. Commonly available voltage driver circuits are deficient for driving n-channel MOS RAMs due to insufficient peak voltage and extended rise time. The apparatus, without requiring an additional voltage power supply or modifications to the memory system environment, effectively increases an internal drive voltage which results in the desired performance characteristics for driver circuits.

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N. Abington, MA, United States of America

Edwin P Fisher