Mips Computer Systems, Inc.

Intel Corporation

Edwin L Hudson

Thomas J Riordan

Earl A Killian

Paul S Ries

Stephen L Smith

Mark G Johnson

A system for synchronizing the operation of a CPU and coprocessor operating from a common clock signal includes a first voltage controlled delay line connected to receive the clock signal and delay it by a fixed time interval before supplying it to one of the CPU or coprocessor. A second voltage controlled delay line is connected to receive the clock signal and delay it by an adjustable time interval before supplying it to the other of the CPU or coprocessor. The time interval of the second delay line is determined by the potential of a control signal generated from a phase locked loop circuit coupled to the output terminals of the CPU and coprocessor.

Variable delay line phase-locked loop circuit synchronization system

A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.

Processor controlled interface with instruction streaming

CMOS buffers are described which provide compatibility between a CMOS circuit and ECL circuits. The input buffer includes a comparator referenced to the V.sub.BB potential. This potential is developed on the CMOS chip with bipolar transistors integrally formed during the CMOS processing. The output buffer also utilizes a bipolar transistor and includes overshoot protection circuitry to prevent overshooting in the transition on the output line from a high potential to a low potential.

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Santa Clara, CA, United States of America

Edwin L Hudson